DigiTimes has published the first part of a three-part interview with Soitech process engineering manager Christophe Maleville. This particular section of the interview focuses on the challenges facing the semiconductor industry as manufacturing technology moves to ever-smaller processes, and what, specifically, SOI technology brings to the table. Dr. Maleville is, as one might expect, enthusiastic about the benefits of SOI and sSOI (strained Silicon on Insulator). When asked whether the use of SOI wafers can lower power consumption, he responded as follows:
I would like to refer to some published data from AMD. AMD has announced it is moving to SOI for 90-nanometer and below technologies. Such results show a 38% improvement in dynamic power and a 46% improvement in static power. This means you can expect an overall improvement of close to 50%, using SOI.Other topics covered include the use of SOI to improve the number of devices that can be built per wafer, the manufacturing transition from 300mm to 450mm wafers, and SOI's compatibility with next-generation 65nm and 45nm lithography.
These are representative figures for processors that would normally have a power consumption of over 100-150W. That represents a significant solution to the problem of the "thermal wall." Previously, the thermal wall has imposed severe limitations on any further shrinking of design geometries. Now, we think that SOI is really enabling the extension of Moore's Law.
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