Intel revises Yonah code names, delays Montecito

— 11:23 AM on November 17, 2005

DigiTimes reports today that Intel has revised its code names for Yonah. According to the article:

All 65nm Yonah CPU lines will be designated by one letter followed by four numbers, the makers said. The four numbers following the "E," "T," "L," and "U" TDP designation will begin either with a "1" or "2," with "1" representing single-core products and "2" dual-core ones, the makers explained.
The same article also contains an update on Intel's dual-core Itanium, code-named Montecito. Montecito was originally projected to arrive in late 2005 or early 2006, run on a 667MHz FSB, and possibly clock as high as 2.4GHz—all while consuming a mere 100W of power, thanks to improved frequency and power management technologies (codenamed Foxton and DBS). It seems that a significant number of these features are now gone or radically scaled back. Not only are power management issues threatening to postpone the CPU's launch until the middle of 2006, but Intel has announced that the chip won't feature the advanced power or frequency management technologies it was originally slated to use. This info corroborates The Inquirer's report that Montecito will launch at a 1.6GHz frequency, a 400MHz FSB, and a smaller L3 cache.
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