Intel discusses on-chip memory controllers

— 6:48 PM on March 8, 2006

Intel CEO Paul Otellini discussed the company's rationale for not integrating the memory controller in its next CPUs at IDF today. According to Otellini, Intel's Next-Generation Micro Architecture (NGMA) Core chips' larger cache—reportedly between 2MB and 4MB—should speed up memory access in a fashion similar to an integrated memory controller. Otellini also points out that integrating a memory controller would introduce compatibility and upgrading restrictions, as the CPU would be bound to a particular type of memory. Finally, he states that an integrated memory controller would take up precious die space, reducing the number of CPUs Intel could fit onto a single wafer.

While Otellini's first two rationalizations make sense, we should point out that an integrated memory controller might decrease the need for such a large amount of cache. This could secure enough die space to include a memory controller without increasing die area significantly, if at all. For reference, the 4MB cache on Conroe appears to take up roughly 50% of the chip's die area, whereas the memory controller and DDR interface on a dual-core Opteron only consume about 12% of the total die area. Of course, Otellini fails to mention that Intel's chipset business may make the company less enthusiastic about moving a major north bridge component over to the CPU.

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