Quad-core Opterons to have shared L2 cache?


— 11:38 AM on May 3, 2006

Chinese site HKEPC says it has gotten its hands on a new AMD roadmap (translate here) that sheds a little more light on the company's plans for quad-core chips. According to the roadmap, AMD will launch its first quad-core server processor under the "Deerhound" code name in the second half of 2007. The chip is listed as being built on 65nm process technology and using AMD's 1,207-pin Socket F with dual-channel DDR2 memory. More interesting is the "shared L2 cache" tidbit under the Deerhound entry. If true, this arrangement would be a departure from AMD's current dual-core design with separate L2 caches for each core. It may also not be unlike Intel's upcoming dual-core Woodcrest, Conroe, and Merom designs that should all feature between 2MB and 4MB of shared L2 cache. Paradoxically, Intel's own quad-core Kentsfield and Clovertown chips may not share their L2 caches, since they're apparently built off two separate dies in the same package. Reports claim those processors will ship in the first quarter of 2007, however, which would be a little earlier than these quad-core Opterons.

Aside from Deerhound, the roadmap also lists a quad-core "Greyhound" desktop chip for the first half of 2008. This processor is said to feature shared L2 cache, as well as DDR2/DDR3 and HyperTransport 3.0 support. The HT 3.0 specification was recently announced and is expected to provide up to 20.8GB/s of full-duplex interconnect bandwidth.

Finally, the roadmap shows a "Zamora" quad-core server chip with FB-DIMM and HT3.0 support for the second half of 2008. FB-DIMMs will bring serial signaling and higher memory capacities—reportedly as high as 192GB—to high-end servers. On the Intel side, FB-DIMM support is expected to arrive as early as May or June of this year with the Bensley platform.

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