— 11:24 AM on May 16, 2006

Apologies for being kind of scarce around here lately. I was traveling last week—went to Oregon to visit Intel and check out their new Bensley server platform. The highlight of that trip was the chance to test Intel's new Woodcrest processors on this platform. I had time to do a fair amount of testing, and now I'm back in the labs trying to duplicate the conditions of those tests on Xeons and Opterons. I can't give you performance numbers just yet, but I can say Woodcrest is looking very fast indeed. The results have done nothing to disabuse me of the notions our Conroe performance numbers established about Core microarchitecture performance.

In fact, I think the Core architecture may be even more advantageous in the server/workstation space for various reasons. For one, Woodcrest's true dual-core design with its shared L2 cache presents only a single load on the front-side bus for each chip, while current Paxville and (imminent) Dempsey Xeons require two bus loads per socket. The additional bus loads increase coherency traffic and dictate slower bus clocks. Woodcrest's shared L2 cache, by contrast, may be even more elegant for SMP than AMD's dual-core Opteron design.

There's more, but I should save it for the full article. The next week will be a very busy one, but we should have a lot of good stuff for you soon.

Tip: You can use the A/Z keys to walk threads.
View options

This discussion is now closed.