As Intel's revelation of a tera-scale floating-point chip with 80 processing cores most vividly underscored, highly parallel processing is definitely heating up, whether it be in CPUs, GPUs, or custom accelerator chips. One gets the sense that the very shape of the industry could be altered radically depending on how these things shake out. What follows is my summation of Intel's processor technology-related revelations at IDF, many of which touched on that theme in one way or another.
Intel's new tick-tock rhythm
One of the things that may have gotten lost in the hubbub over the new Core microarchitecture is Intel's intention to modify fundamentally the way it refreshes its processor designs. The company's new goal is to impose a very specific cadence to CPU development that's predicated on the implications of Moore's Law and an imperative to deliver regular microarchitectural advances.
Moore's Law, of course, predicts that the number of transistors possible on a chip will double roughly every two years. Now that multi-core processors have arrived, one can probably expect the number of cores on a chip to double when transistor budgets do, at least for the foreseeable future.
Alongside that, Intel hopes to deliver process technology advances out of sync with major microarchitectural changes in what it calls a "tick-tock" cadence, as the slide below illustrates.
The move from 90 to 65nm is an example of this pattern in practice. The Core Duo processor was the first 65nm processor in its family, but it wasn't a radically new design. The Core Duo's, er, processing core was derived from the 90nm "Dothan" Pentium M. Core Duo was largely a die shrink, a doubling of the number of cores onboard, and some relatively minor enhancements to the processing core itself. That was the first "tick." The Core 2 Duo was "tock"an extensively revised CPU microarchitecture produced with the same 65nm fabrication process.
Next on the roadmap, as you can see, is "Penryn," a 45nm shrink of the Core microarchitecture slated to get some tweaks here and there. As Intel's Mooly Eden put it, the goal with process shrinks is to do only low-risk "local surgery" on the processor cores in order to avoid complicating the process transition. Once the 45nm process has been established, then "Nehalam" will come with a substantially new microarchitecture. The interval between each "tick" and "tock" should be approximately 12 months. That means we're looking at the prospect of major microarchitectural innovations from Intel every two yearsa very aggressive roadmap indeed. If all goes according to plan, we should see the "Gesher" processor four years from now. Based on a 32nm process, Gesher will likely have eight cores per chipand possibly 16 cores in a dual-chip package. Each of those cores should be based on a microarchitecture two full generations beyond the Core 2 Duo.
A glance at the roadmap
This "tick-tock" declaration actually tells us more about Intel's future plans than the official roadmap slides they were showing at this IDF.
Intel's desktop roadmap reveals very little we didn't already know, with few specifics beyond the names Penryn and Nehalem. Paul Otellini revealed more detail in his opening keynote last week, claiming that the first 45nm microprocessor design (presumably Penryn) will be completed next quarter, with 45nm products scheduled to ship in the second half of 2007.
The official server roadmap may be even less specific than the desktop one. Intel did finally make official the new Xeon UP platform, a single-socket server config to be populated by the Woodcrest-based Xeon 3000 series and the Clovertown-based Xeon 3200 series, along with their companion chipsets. In the "DP" server space, the impressive Bensley platform will continue its run for quite some time, playing host to the "Clovertown" quad-core processors now known as the Xeon 5300 series. Both Xeon UP and DP platforms will get "future processors" after Clovertown, at least one of which will presumably be a Penryn derivative.
We know a little bit more about the plans for the higher-end Xeon MP. The "Caneland" platform will replace today's quad-socket, dual-bus arrangement with a four-socket layout that has point-to-point connections to each of the four sockets. Caneland's Clarksboro chipset will also feature a bus snoop filter with a 64MB cache, intended to cut the bandwidth needed on the bus. One of the processors that will drop into Caneland's four sockets will be the chip code-named "Tigerton," a Core microarchitecture-based CPU that will follow in the mold of the Xeon 7100 series. Tigerton will have quad cores and, one can infer, a large amount of L3 cache onboard like the Xeon 7100.
I'm sure Intel filled out a few more details of its roadmap during the week, but I didn't have a chance to ask penetrating questions about some of the roadmap's ambiguities. Regardless, we didn't get an incredibly specific look into the future this time around, no doubt in part because Intel is much more comfortable with its current position than it was at previous IDFs.
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