Pricing and availability
Even with all of these chip-level changes, the biggest news of the day may be the advent of Opterons with higher clock speeds and lower prices. The refreshed Shanghai lineup now looks like so:
|Model||Clock speed||North bridge
All of the new Opterons, ranging from 2.3 to 2.7GHz, fit into the same 75W thermal envelope, according to AMD's "ACP" rating method (which it insists is the best analog to Intel's TDP numbers, though Intel would disagree.) Clock speeds overall are up, and notably, north bridge clocks participate in that advance. I say that's notable because the north bridge clock governs the L3 cache, as well, which has a pretty direct impact on overall Opteron performance.
AMD expects all of the products above to be available now. Conspicuous by their absence are low-power HE and higher-speed SE derivatives of Shanghai. AMD intends for these HE and SE parts to fit into their traditional 55W and 105W thermal envelopes, respectively, when they arrive in the first quarter of next year. With the additional power headroom, the SE parts could quite possibly reach 3GHz, although only time will tell.
The Opteron's next steps
The improvements in Shanghai sound pretty good, but many folks are still asking exactly what AMD will do in order to counter Intel's Nehalem, which promises a similar system architecture andby all current indications, at leasthigher performance per core and per socket. Interestingly enough, AMD does have some credible answers to such questions, and it has disclosed quite a bit of its future Opteron roadmap in response. Here's a quick overview of the basic plan:
Not noted above is the planned release of HyperTransport 3-enabled Opterons next spring. After that, the next big change will be the introduction of the Fiorano platform in mid-2009. Fiorano will be the first Opteron chipset based on the core-logic technology AMD acquired when it purchased ATI. That chipset will be comprised of the SR5690 I/O hub and the SP5100 south bridge. Fiorano will retain compatibility with Socket F-type CPUs, but will add several noteworthy enhancements, including full HyperTransport 3 and (at last) PCI Express 2.0, complete with support for device hot-plugging. As one would expect, Fiorano will support AMD's IOMMU technology for fast and secure hardware-assisted virtualization of I/O devices.
Fiorano will be scalable from 2P to 4P and 8P systems. As you can see in the diagram above, 4P Opteron systems will not be fully connectedthere will still be two "hops" from one corner of a 4P system to the opposing corner. Also notable by its absence is support for DDR3 memory. Although the desktop Phenom II is expected to make the move to DDR3 in early 2009, the Opteron won't follow until it makes a socket transition in 2010.
Before that happens, some time in late 2009, the Opteron lineup will get a boost with the release of a six-core processor code-named Istanbul. This 45-nm chip should look very much like Shanghai, but with two additional cores onboardsame 6MB L3 cache, same DDR2 memory controller, still HyperTransport 3. For certain applications, a six-core Opteron could conceivably be a nice alternative to Intel's quad-core, eight-thread Nehalem-based Xeons, although by the time Istanbul arrives, Intel may be reaching new milestones in its own roadmap.
Then comes the transition to the new G34 socketthe funky elongated, rectangular socket you may have seen in some reportsin 2010. This socket will bring a major infrastructure refresh for the Opteron. DDR3 support will come in with a bang; each socket is expected to support four channels of DDR3 memory. Also, the maximum number of HyperTransport 3 links per chip will rise from three to four, potentially enabling fully connected 4P systems.
Interestingly enough, all of the changes here will apparently be the result of modifications to the physical socket and to Opteron processors. Although AMD has given the new platform a code name, Maranello, it uses the same two core-logic chips as Fiorano.
The new processors will come in two distinct flavors: Sao Paulo, with six cores and 6MB of L3 cache, and the oh-so-cleverly named Magny-Cours, with a whopping 12 cores and 12MB of L3 cache. We don't yet know whether or how these cores will be enhanced compared to Shanghai Opterons. Both chips will be manufactured with 45nm process tech, and the basic cache hierarchy on the Opteron will remain the same, with an exclusive L3. AMD will add additional smarts to these chips, though, in the form of a probe filter (or snoop filter) that will reduce cache coherency management traffic. Also, much like Nehalem, these processors will feature on-chip power management and thermal control capabilities, including the ability to raise and lower clock speeds based on thermal control points.
Beyond that, things become foggy. We know that AMD's spun-off manufacturing arm, temporarily dubbed "the foundry company," has plans to introduce two advanced 32-nm fabrication technologies in the first half of 2010, a high-performance process using SOI and a low-power process using high-k metal gates. Meanwhile, AMD is working on a next-generation CPU microarchitecture code-named "Bulldozer," about which we know very little. Early information on Bulldozer suggested it would initially tape out on a 45nm process, but more recent rumblings from AMD suggest Bulldozer has been pushed backthe desktop variant to 2011and may be a 32nm part.
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