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A new platform, too
Of course, this sweeping set of changes brings with it a host of platform-level alterations, not least of which is the modification of the role and naming of what has been traditionally called the north bridge chip, or the memory controller hub (MCH) in Intel's world. Say hello, instead, to the I/O Hub, or IOH.


A block digram of the Tylerburg chipset. Source: Intel.

The new Xeons' first IOH has been known by its code name, Tylersburg-36D, and will now be officially called the Intel 5520 chipset. True to its name, this IOH is focused almost entirely on PCI Express connectivity, with one QPI link to each of the two processors and a total of 42 PCIe lanes onboard—36 of them PCIe Gen2 and six Gen1. Those lanes can be apportioned in groups of various sizes for specific needs. Tylersburg also has an ESI port for connecting with an Intel south bridge chip, one of the members of the ICH9/10/R family; these chips provide SATA and USB ports, along with various forms of legacy connectivity.

Tylerburg's dual QPI links open up the possibility of dual IOH chips, which Intel has decided to enable for certain configurations. In this scenario, each Tylersburg chip is linked via QPI to a different CPU, and the two IOH chips are linked via QPI, as well. The primary IOH chip handles various system management and legacy I/O duties, while the secondary one simply provides 36 additional lanes of PCIe Gen 2 connectivity, for a total of 72 lanes in the system (plus six Gen1 lanes). That's a tremendous amount of connectivity, but it's in keeping with the platform's high-bandwidth theme.


Two large coolers and one DDR3 DIMM per channel in our test rig


The new Xeons' LGA1366-style socket


Nehalem-based Xeons come in a much larger package (left) than the prior Xeon generation (right)

The new Xeons drop into a new, LGA1366-style socket that looks, unsurprisingly, just like the Core i7's. The CPU itself is housed in a larger package, as well, that dwarfs the Harpertown Xeons and their predecessors.