We're pleased Llano is capable of supporting the latest in DDR3 memory standards, and we're happy to be able to demonstrate some performance gains when the APU is used in conjunction with faster RAM. However, I think we can say with some certainty that Llano's overall competitive picture doesn't change substantially when higher speed memory is added to the mix.
The CPU cores on this chip are based on, uh, a proven-technology microarchitecture, and that architecture doesn't appear to extract much additional instruction throughput from a higher-performance memory subsystem. One might expect Llano, with no L3 cache, to benefit more than most processors from faster RAM, but these days, it seems CPUs with larger caches and aggressive pre-fetching make the best use of additional memory bandwidth when it becomes available.
More unexpectedly, even Llano's IGP doesn't churn out substantially higher frame rates in the presence of 1866MHz memory. At its relatively low core clock speed of 600MHz, the Sumo IGP appears to be getting most of what it needs from 1333MHz or 1600MHz memory.
Despite these results, we do expect memory bandwidth to become ever more critical as CPUs with integrated graphics—or APUs, if you must—mature. Recall that AMD has done little in the way of true architectural integration with Llano, instead opting to focus on reducing power consumption (especially at idle) and getting a product to market quickly. AMD's next APU in this segment, code-named Trinity, should combine the brand-new Bulldozer microarchitecture with a Cayman-derived, second-generation DX11 Radeon IGP. That chip might also feature Sandy Bridge-esque architectural integration, with features like a high-speed internal bus and a shared last-level cache. Such changes should make this next APU much hungrier for memory bandwidth—and much more capable of taking advantage of it—than this first attempt.
69 comments — Last by flip-mode at 5:17 PM on 07/22/11
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