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The next Atom: Intel's Silvermont architecture revealed


All-new architecture shoots for superior single-threaded performance
— 12:00 PM on May 6, 2013

Intel's Atom processor debuted five years ago as the first x86-compatible CPU from Intel tailored explicitly for low-power operation. At that time, the iPhone was less than a year old, and Asus had only recently introduced the first-generation Eee PC. Intel was talking about a new class of products, known as MIDs or "mobile Internet devices," as the natural home for the Atom.

You know what happened next. Without robust touch interfaces, MIDs never took off. Instead, the netbook craze came and went, and tablets became an outright phenomenon. Smartphones grew in size, tablets shrank, and "phablets" bridged the gap between the two.

Something else happened along the way—or perhaps didn't. The Atom never really replicated its initial success in netbooks among other consumer devices. Intel revved the various incarnations of the Atom, reducing power envelopes and physical footprints. It integrated ever more functionality into true SoC products like Moorestown, aiming for smartphones, and won some business along the way. But the Atom has captured only a handful of high-profile design wins among smartphones, and the few Windows 8 tablets based on the current Clover Trail platform have seen only modest adoption to date. Instead, the great majority of mobile computing devices for consumers are based on ARM's CPU technology—or are compatible with it.

Another thing that didn't happen is a change to the Atom's microarchitecture. Intel wrung out some performance and power efficiency gains through integration, improved process tech, and higher clock speeds, but the CPU cores themselves remained largely the same.

That fact seems a little odd, since it's been clear for several years that Intel views ARM as its biggest competitive threat. But the world's biggest chipmaker hasn't been idle. It has been pushing its highest profile Core processors into ever-lower power envelopes, and the hotly anticipated Haswell chip is expected to hit the market early next month with TDPs reaching down to 10W or less. Meanwhile, the firm's Austin-based design team has been hard at work on a clean-sheet redesign of the Atom microarchitecture, code-named Silvermont. Today, we can reveal the first details about Silvermont, and they look very promising indeed. Intel is claiming that this new architecture, when combined with its 22-nm fabrication process, will enable chips that offer three times the performance of the prior-generation Saltwell Atom with "5X lower" power consumption.

Silvermont isn't just a new architecture; it's also the beginning of an accelerated update schedule for Intel's low-power processors. Going forward, the Atom will be getting the same sort of "tick-tock" cadence that Intel has employed to great effect with its Core processors. As before, the Atom will be shrunk to a new process node roughly every other year. In between, the CPU architecture will be revised, as well. As you can see in the image above, "Airmont" will be a shrink of Silvermont to 14 nm. After that, we should see a revamped microarchitecture on this same fab process, although Intel isn't ready to reveal its codename.

It goes without saying, perhaps, but the move to a tick-tock cadence in the low-power segment means Intel is dead serious about winning in this part of the market.

Before that new plan can take hold, Intel has to deliver Silvermont-based products. That's slated to begin happening later this year, in several system-on-a-chip (SoC) configurations intended for different market segments.

The Bay Trail SoC will replace Clover Trail and offer more than double the compute performance for tablets. Bay Trail should also make its way into entry-level notebooks and desktops. It's slated to arrive inside of new systems ahead of the holiday buying season. Merrifield, the phone chip, should start shipping to smartphone makers by year's end, and products based on it should be announced in the first quarter of 2014. Avoton is targeted at micro-servers and is already sampling, with an official launch coming in the second half of 2013. Rangeley, the communications infrastructure part, will also launch in the year's second half. Intel intends to address other parts of the embedded CPU space, such as automotive infotainment systems, with additional Silvermont-based platforms that have yet to be announced.

The Silvermont story
Despite driving its Core architecture into power envelopes of 10W and lower, Intel is making a big commitment to the separate development of a low-power architecture going forward, because the Atom can go places Core cannot: into power envelopes measured in hundreds of milliwatts, into smaller physical footprints, and into much lower-cost platforms. The list of SoCs being created with Silvermont tells that tale. Necessarily, then, this low-power architecture must accept a different set of compromises than Core, with a focus on operating at very low voltages using a more modest transistor budget.

Within the scope of these limitations, Silvermont's architects have reached for a much higher performance target, especially for individual threads. The big news here is the move from the original Atom's in-order execution scheme to out-of-order execution. Going out-of-order adds some complexity, but it allows for more efficient scheduling and execution of instructions. Most big, modern CPU cores employ OoO execution, and newer low-power cores like AMD's Jaguar, ARM's Cortex-A15, and Qualcomm's Krait do, as well. Silvermont is joining the party. Belli Kuttanna, Intel Fellow and Silvermont chief architect, tells us the new architecture will achieve lower instruction latencies and higher throughput than the prior generation.

Interestingly, Silvermont tracks and executes only a single thread per core, doing away with symmetric multithreading (SMT)—or Hyper-Threading, in Intel's lingo. SMT helped the prior generations of Atom achieve relatively strong performance for an in-order architecture, but the resource sharing between threads can reduce per-thread throughput. Kuttanna says SMT and out-of-order execution have a similar cost in terms of die area, so the switch from SMT to OoO was evidently a fairly straightforward tradeoff.

This decision makes a lot of sense in the context of Silvermont's new fundamental building block, which is a dual-core "module" with a single, shared L2 cache. Intel talks of the two cores being "tightly coupled," echoing the way AMD describes the dual-core module used by its Bulldozer architecture, but no logic is shared between the two cores—just the cache. The module can scale up to four on a chip, or eight cores on a single SoC. With core counts like that possible, Silvermont-based systems ought to exploit thread-level parallelism sufficiently without the use of SMT.

Silvermont will have additional opportunities for parallelism thanks to its expanded ISA support, which brings Intel's low-power architecture largely up to parity with Westmere-class desktop processors. That means support for the SSE4.1 and 4.2 extensions along with AES-NI encryption. AVX isn't supported, which is no great surprise given the requirements and Atom's mission in life. The architecture does include expanded virtualization support, including extended page tables and the rest of Intel's VT-x2 suite, which could benefit those SoCs targeted at micro-servers. Another new feature is real-time instruction tracing, to aid with debugging.

The dual-core Silvermont module talks to the rest of the chip via a new system fabric architecture, which should offer higher transfer rates and easier integration than the internal front-side bus used in prior Atoms.