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Intel aims to reinvent the data center


An aggressive strategy marks the beginning of an new era
— 9:32 PM on July 29, 2013

Last week, Intel hosted an event for press and analysts where it provided some updates on the state of its data center business. Such events are usually staid affairs where the world's largest chipmaker offers some details about the latest incremental updates to its Xeon processors and perhaps a scrap or two about Itanium, just for comic relief. After all, servers are very serious business, and one wouldn't want to project disruptive intent—especially not Intel, the firm that has dominated the traditional server business in recent years, reaping handsome profits in the process.

Yet Intel did precisely the opposite of what you might expect. Diane Bryant, Senior VP and GM of the Datacenter and Connected Systems Group, used her opening keynote to project a somewhat radical vision of the data center of the future. In this vision, nearly every component of the data center—from servers to switches to storage to network appliances—will be re-architected to offer more flexibility and configurability.

Today's networks, with manual provisioning and distributed control of resources, will give way to software-defined networks that can be controlled via a single, centralized interface. Those networks, from core switches to cellular base stations, will run in sophisticated software on high-volume Intel hardware. In storage, expensive SANs will be replaced by multi-tier storage services. Those services will allocate data to the appropriate tier in the network—from high-cost, high-speed SSDs through efficient cold-storage systems populated by spun-down hard disk drives—automatically, in response to application request patterns. Servers won't be spared in the transformation, either. Instead of today's arrangement, where discrete servers are carved up into virtual machines, the rack itself will become the basic unit of data center computing. The various pools of compute, memory, and storage capacity in each rack will be provisioned in software-defined servers, according to application needs.

As you might have gathered, this future data center is much better instrumented. That is, it's aware of how applications are using the available resources. Combine that awareness with the ability to reallocate those resources dynamically, and admins should be better able to optimize the data center, eliminating bottlenecks while making fuller use of each server than in the past.

Sounds good, doesn't it? But how will Intel make it happen? Is it developing some sort of comprehensive solution for the automated data center of tomorrow?

Not exactly. Intel's Jason Waxman, GM and VP of the Cloud Platforms Group, spoke next, and he laid out some of the details of Intel's plans. As he did so, it became clear that Intel will continue to be itself: a supplier of the chips, platforms, and tools. The firm will enable a host of different partners to build the sorts of solutions Bryant described.

Still, Intel's intention to attack other areas of the data center, beyond the center of the rack where the servers sit, is a major change in strategy—and the chips, platforms, and tools to make it happen are deep into development already, with some key products due to ship in the second half of this year.

Those products include Avoton and Rangeley, a pair of low-power systems-on-a-chip (SoCs) based on the brand-new Silvermont architecture Intel announced a couple of months ago. Silvermont is the next incarnation of the microarchitecture that underpins Intel's Atom processors. The Avoton and Rangeley SoCs are targeted specifically at data center deployments, including networking, storage, and the emerging category of microservers for cloud service providers.

Surprisingly, Waxman revealed quite a bit about Avoton and Rangeley in his presentation, including the slide above that shows the basic chip setup. These 22-nm chips each have four dual-core Silvermont modules for a total of eight cores, and they include 16 lanes of second-generation PCI Express connectivity. These are true SoCs with a full complement of interconnects on board, including SATA, USB, Gigabit Ethernet, and legacy PC I/O. The Rangeley variant includes an additional hardware block for the acceleration of cryptography, a necessary feature for its expected role in communications solutions.

Avoton and Rangeley are clearly not just phone and tablet SoCs repurposed to serve niche roles in the data center. They support true 64-bit memory addressing, protection of memory via ECC, and Intel's ISA extensions for virtualization (up to the level of Westmere-based Xeons). With up to 64GB of capacity—via dual channels of DDR3-1600 memory—they also support quite a bit of physical RAM per node.

Intel says Avoton and Rangeley have been sampling to customers for months, and final products are expected to ship later in 2013. Although some ARM partners like Calxeda already have products in the market, Avoton and Rangeley should be beefier than the current low-power server SoCs in terms of core counts, connectivity, and true 64-bit memory addressing.

Intel is claiming big gains in performance and power efficiency for the Avoton/Rangeley-based Atom C2000 series versus the prior-generation Atom S1200 series. Some of those improvements come courtesy of the more potent Silvermont CPU microarchitecture, but I believe higher core counts, faster networking, and larger memory capacity also play a role in those claims.

In addition to pulling back the curtain on a lot of details about Rangeley and Avoton, Waxman announced that Intel is developing two more SoCs for release next year. As part of Intel's new tick-tock development cycle for the Atom, a chip code-named "Denverton" will succeed Avoton at some point in 2014. Denverton will employ the same basic CPU architecture, but it will be built on Intel's 14-nm fabrication process with the firm's second generation of 3D transistors. (It's a bit jarring to think how far ahead of the competition Intel may be at that time. For instance, AMD's Seattle chip based on ARM Cortex-A57 cores is slated for the second half of 2014, and it's expected to be built on a 28-nm fabrication process that uses a planar transistor structure.)

That's only one of the SoCs. The other one will be a server-focused SoC based on Broadwell, the 14-nm follow-on to Intel's Haswell processor. As you may know, Haswell has been tuned extensively for low-power operation in ultrabooks. Broadwell should extend that trajectory further, which makes it potentially a very nice fit for those spots where an Avoton might do but a little more computing power would be preferable. We don't know much yet about this Broadwell-based SoC, but Waxman confirmed that it will be a single chip with integrated I/O, storage, and networking. It will likely target many of the same segments as Avoton and Rangeley, including microservers, networking, and the like. Waxman didn't offer any specifics about power envelopes, but Haswell already stretches from under 5W to over 80W. I'd expect the Broadwell SoC to play at least in the lower half of that range.