Intel is a company famously driven by paranoia, but the threat it now faces requires no special effort to see. Smartphones have grown and morphed into tablets, and together, these two new categories of devices have taken a big bite of out the consumer computing market. Laptop sales in particular have gone soft as tablets have grown in popularity.
The vast majority of these tablets are based on CPU technology from ARM. Intel's position in the PC market couldn't be much more commanding right now, but that alone is suddenly looking like a wobbly foundation for the future. The firm has attempted to address the mobile market with successive generations of its Atom processors, but those haven't seen much success. Now, a rising urgency has prompted Intel to double down on its efforts, much as it did when the Pentium 4 was struggling to keep pace with AMD's chips. For the first time, the years-old Atom microarchitecture has been completely rebuilt, and Intel has committed to bringing its methodical tick-tock development cadence to the Atom lineup going forward. Architectural refreshes will be interleaved with new process technology in a series of yearly updates.
Each of these updates will produce a host of Atom-based systems on a chip (SoCs) for different markets. The eight-core chip known as Avoton is headed for microservers and storage applications. Its near-identical twin, Rangeley, will be deployed in network and communications devices. An SoC called Merrifield will tackle the smartphone space.
Our concern today is the chip intended for tablets and convertible laptops, which is code-named Bay Trail. We've known for a while that Bay Trail was coming and that it would be based on the new Silvermont CPU microarchitecture. Beyond that, details have been scarce. Now, as the Intel Developer Forum opens in San Francisco, Bay Trail is making its first public appearance. We have extensive details on the SoC's basic architecture—and a first look at its performance.
An overview of the SoC
Bay Trail truly is a system on a chip, with a full complement of the components needed for laptops and tablets. It is in many ways similar to the Avoton chip we covered last week, but Bay Trail is scaled back for a smaller footprint, lower power use, and lower costs.
Like Avoton, Bay Trail is fabricated on a special variant of Intel's 22-nm manufacturing process that's been tuned for SoCs. This process has some of the finest geometries in the industry and is the first to implement a tri-gate or FinFET-style transistor structure. The foundries that produce ARM-based SoCs for competitors like Qualcomm and Nvidia are arguably at least a couple of years behind Intel on this front—and Intel is already talking about making the transition to 14 nm next year.
Below is a simplified block diagram of the Bay Trail SoC. We can use it as a starting point and add some detail to get a pretty good picture of what's included in the silicon.
The four CPU cores probably deserve top billing. The Silvermont architecture clumps two cores together into a single "module" that functions as a basic building block. Each module has 1MB of L2 cache shared between its two cores, and Bay Trail integrates two of these modules. We've already covered the Silvermont microarchitecture in some depth. The big change here is a focus on higher per-thread performance. Silvermont does away with symmetric multithreading (aka Hyper-Threading) and instead adds out-of-order execution in an effort to extract more parallelism out of sequential code. This change is eminently sensible given that the performance of one or two main threads often determines the user experience in tablets—and that even a relatively small chip like Bay Trail can execute four hardware threads without SMT.
At the center of the "north complex" above is an orange block known as the Silvermont system agent. The SA is the traffic cop that directs the flow of data between the major functional blocks of Bay Trail's north complex. We know from our look at Avoton that the system agent employs a crossbar architecture, like a network switch, to ensure high-bandwidth communication from any one component to any other. The SA is linked to the Silvermont modules using a point-to-point interface known as IDI; it's the same interface Intel has used in its big cores since Nehalem.
Hanging off of the system agent are Bay Trail's dual memory controllers, each capable of talking to a single channel of DDR3 or DDR3L memory. The chip's peak possible memory bandwidth is about 17 GB/s when both channels are equipped with 1066 MT/s memory. I assume this relatively low memory speed is due to power considerations. Some variants of Bay Trail will support only a single memory channel, and in that case, the DRAM can run at 1333 MT/s.
With both channels populated, the SoC's maximum memory capacity is only 4GB, another indication of this platform's power and size constraints.
One of the largest areas on the Bay Trail die is dedicated to graphics. Interestingly, Intel has jettisoned the Imagination Tech graphics it used in prior generations of mobile SoCs in favor of its own in-house Intel HD Graphics. This is essentially Intel's latest graphics tech, and it's the same generation used in larger Ivy Bridge CPUs. (Haswell's graphics hardware is similar but tweaked for higher efficiency.) Intel says Bay Trail supports the latest graphics APIs, including DirectX 11 and OpenGL ES 3.0. We know from Ivy Bridge that this graphics core supports high-precision datatypes and is capable of general-purpose computing via OpenCL.
Of course, the unit count has been scaled back for this mission. Haswell desktop processors like the Core i7-4770K have 20 graphics executions units, or EUs. Bay Trail has only four EUs. For those keeping score at home, each of those EUs is SIMD32, equivalent to eight "shader processors" in the world of big GPUs, so Bay Trail has the equivalent of 32 SPs. The graphics clock speed varies but can reach as high as 667MHz in optimal conditions. According to Intel, that should add up to three times the performance of Clover Trail, its prior-generation tablet SoC.
Bay Trail's video processing block can decode an alphabet soup of modern video formats, including H.264, VC1, MPEG2, and MPEG4. The hardware can also encode video in a couple of formats. H.264 encoding is accelerated fully, while MPEG2 encoding is handled via a hybrid approach, with key portions like motion estimation offloaded to hardware and other parts handled in software.
The display controller is fairly beefy, as it will need to be in order to drive the high-density displays now popular in tablets. The chip has two matching display outputs that conform to a range of standards, including HDMI 1.4, DisplayPort 1.2, DVI, and eDP 1.3. Each one can drive a display with a resolution of up to 2560x1600 at a refresh rate of 60Hz.
Oh, and here's a feature with a classic Intel-style name: Display Power Saving Technology, or DPST for short. This feature combines dynamic backlight dimming with image modification (brightening up the images, basically) in order to reduce the power consumed and the heat produced by the display backlight—presumably without the end user noticing.
The final feature of the north complex is an image signal processor, which controls any onboard cameras and both receives and processes the pixels they capture. Bay Trail's ISP can connect to dual cameras ranging from eight to 13 megapixels, and it has sufficient throughput to handle 1080p video at 60 FPS. A host of photographic features are included, including auto-exposure, auto-focus, auto-white balance, video stabilization, and a burst shooting mode.
That's about it for the SoC's north complex. The lower portion of the diagram above covers the south complex, which handles all sorts of lower-bandwidth I/O. In our briefing, Bay Trail's chief architect, Rajesh Patel, wasn't willing to divulge too many details about the nature of the switching fabric that connects the south complex to the system agent. We strongly suspect it's the same Intel Optimized Switching Fabric, or IOSF, used in Avoton. IOSF is software-compatible with PCI Express, and it's employed in Haswell and all of Intel's current discrete platform controller hubs.
This interconnect is noteworthy because it's an Intel-specific standard that allows the re-use of various logic blocks across a range of chip designs—and because it signals a move within Intel toward the SoC-style methods used to create many ARM-based chips. We learned in our Avoton briefing that "everything being developed now" at Intel makes use of IOSF.
The south complex offers links to a bunch of tablet- and PC-style interfaces. The biggest highlight may be the inclusion of USB 3.0 for truly speedy external connections. Bay Trail supports the USB "On-The-Go" spec, as well, so systems based on it should be able to act either as hosts (to devices like iPods) or as clients (to desktop PCs and the like.) Conspicuous by their absence are external PCI Express lanes and SATA ports. Primary storage will have to be handled by the eMMC interface, instead.
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