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Samsung's 850 Pro solid-state drive reviewed


3D V-NAND comes to the PC
— 9:00 PM on June 30, 2014

Here we go again. Another Serial ATA SSD is ready for prime time. Like all the others that have been cropping up recently, it combines a familiar controller with next-gen flash memory.

But Samsung's 850 Pro isn't like the others at all.

In most new SSDs, the next-gen flash is just a die shrink of the previous generation. The nanoscale features are smaller, enabling higher bit densities, but the technology is fundamentally the same. The flash memory in the 850 Pro is on a whole other level—32 of them, actually. While traditional NAND sticks to a planar layout, the 850 Pro's V-NAND extends into three dimensions by stacking multiple flash layers on top of one another.

V-NAND is designed to avoid some of the constraints associated with shrinking NAND lithography to ever-smaller process nodes. Samsung claims V-NAND offers higher performance and longer endurance than typical flash, too. Naturally, the 850 Pro follows suit. This baby is billed as not just the fastest SATA drive around, but also the most durable. To underscore that claim, Samsung has given it a 10-year warranty.

So, yeah, the 850 Pro isn't just another Serial ATA SSD. Let's see what makes it tick.

Flash in three dimensions
Before discussing the drive, we should probably start with the flash and the fact that this isn't Samsung's first 3D rodeo. The first generation of V-NAND debuted last August with 24 layers and, eventually, found its way into an accompanying server drive aimed at datacenters and other enterprise applications. The 850 Pro is based on second-gen V-NAND with 32 layers. Samsung tells us "essentially the same equipment" was used to manufacture the new chips, which like their predecessors, are fundamentally different than the planar NAND found in pretty much every other SSD.

Most flash memory is laid out on a single layer. Storage densities are increased by shrinking the lithography, allowing more cells to be squeezed into the same area. More cells per unit area translates to more gigabytes per wafer, effectively lowering the per-gigabyte cost. Those savings are passed along to consumers in the form of lower SSD prices.

For years, flash makers have pursued finer fabrication techniques. They've been very successful, but planar technology is approaching its limits. Patterning becomes more difficult as the feature size shrinks, and packing cells closer together increases the potential for interference between them. 3D NAND skirts both of those challenges by stacking memory cells vertically, a path to higher densities that doesn't involve shrinkage.


Source: Samsung

V-NAND's structural changes run even deeper than its multi-tiered layout. In a traditional planar NAND cell (pictured on the left in the image above), data is stored by trapping electrons inside a floating gate. The gate is conductive, but it's suspended in an oxide insulator that keeps electrons from escaping. The electrons come from the underlying substrate, which sits below a tunnel oxide layer that acts as an insulator. Voltage applied at the control gate causes electrons to tunnel through the oxide layer.

Electrons tunnel into the cell when data is written and back to the substrate when it's erased. As write and erase cycles accumulate, the tunneling process breaks down the oxide layer and leaves stray electrons stranded in it. Eventually, a short can form between the floating gate and the substrate, draining the gate of electrons and eliminating its ability to hold a charge. The cell is effectively dead at this point and must be retired.

Floating gate tech has been around since the 70s, but it's not the only option. Another approach, called charge trap flash, swaps the floating gate for a trapping layer. The same tunneling process is used to move electrons in and out of the cell, but the trapping layer is an insulator, making the cell less vulnerable to erosion of the tunnel oxide. Shorts don't drain the entire cell, just the electrons in the immediate vicinity of the breach.

The inherent short-circuit tolerance of charge trap flash allows for a thinner tunnel oxide layer. Write and erase speeds can improve as a result. The thinner layer also enables lower programming voltages, which can reduce power consumption and slow the breakdown of the oxide layer.

Samsung introduced planar NAND based on charge trap tech way back in 2006. The chip was built on a 40-nm process, and the approach apparently didn't stick, because Samsung's last few generations of 2D NAND have been based on floating gates. But the trapping layer was reborn in V-NAND, where it wraps around a vertical electron channel that spans multiple layers.


Source: Samsung

Despite what my crude frame capture from Samsung's V-NAND promo video shows, the control gate wraps all the way around the cylindrical trap. (The full video is located at the bottom of this page.) V-NAND is three-dimensional right down to its component cells. Those cells are arranged vertically, with "much width of space" between each layer, according to the video. Samsung's V-NAND presentation (PDF) from last year's Flash Memory Summit claims this arrangement is "almost free" of cell-to-cell interference along its vertical word lines. The horizontal bit lines are "interference free," the slides add.

Samsung provided additional details on its first-gen V-NAND during the International Solid-State Circuits Conference earlier this year. Nikkei Technology's coverage reveals several interesting tidbits, including the fact that the chips are fabbed on a 40-nm process. Sound familiar? Samsung apparently intends to keep that feature size as it adds layers, which should prevent patterning issues from standing in the way of higher densities. There's room to scale "more than 5 generations," the firm says, and it eventually expects V-NAND to squeeze 128GB onto a single die.

The initial V-NAND chips used 24 layers to reach 16GB, so Samsung has a long way to go before it reaches the terabit threshold (1Tb = 128GB). The second-gen chips have 32 layers, an increase of 33%, but we're still waiting for confirmation on their capacity per die. Those extra layers could have been used to increase the capacity, but it's also possible Samsung opted to create a 16GB part with a smaller planar footprint. Either way, it looks like the second-gen chips retain the two-bit MLC configuration of their forebears.

Details on the 850 Pro's second-gen V-NAND are a little scarce as I write this. The drive makes its debut at Samsung's SSD Global Summit in Seoul, South Korea today, and I'm at the event to learn more. Hopefully, I'll have additional V-NAND details to share with you soon.

In the meantime, it's worth highlighting a few more attributes of the first-gen chips. Samsung says they write at twice the speed of conventional MLC NAND, consume half the power, and offer "two to ten times" the endurance. Like I said, this is next-level stuff.

The endurance appears to be contingent on the write speed. According to the ISSCC slides, V-NAND can survive 3,000 write cycles at 50MB/s or 35,000 cycles at 36MB/s. That's an order-of-magnitude increase in endurance for only a 28% decrease in performance. Samsung wouldn't elaborate when I asked if V-NAND offers the freedom to choose between higher performance and longer endurance, but it sounds like the company will have more to say on the matter later this year.

Now that we have a better understanding of V-NAND, let's look at how it's implemented in the 850 Pro.