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The future of Moore's Law

Taken together, the better-than-Moore's-Law density improvements Intel claims from its "hyper-scaling" techniques seem to point to another redefining of Moore's Law. Instead of considering its improvements using a rigid two-year cadence, the company suggests that the longer intervals between process nodes combined with the greater-than-2x-improvement in logic density per node should be viewed as averaging out to the expected improvement over time.

Fair enough, I suppose, presuming that Intel's future move to a seven-nanometer process can happen quickly enough and the scaling benefits such a move provides are great enough that the "hyper-scaling" trend continues to hold. In any case, the details Intel has shared about its 10-nm process have me excited for the potential of chips produced on that node. Furthermore, if the company's new MTr/mm² metric is accurate, the company will simply be able to pack far more transistors into a given logic area than its competitors' 10-nm-class processes will.

That said, Intel doesn't seem to be ready to introduce any 10-nm products any time before sometime in 2018 at the earliest. That release window coincides with TSMC's plans to begin producing 7-nm-class products, which could be more competitive on the density metric that Intel is touting. Without setting up electron microscopes and some kind of X-ray tomography system in the TR labs, we can't verify any of these claims independently, but we look forward to the performance and power-saving advancements these new production techniques herald when they do finally yield production silicon.

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