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AMD's Epyc 7000-series CPUs revealed


Zen gets its data center marching orders
— 3:00 PM on June 20, 2017

AMD has been in a data-center desert for many years. Abu Dhabi Opterons marked the company's last serious foray into the market in 2012, and since then, Intel's market share of all server chips has been at least as high as 99.2%. Long-running murmurs of ARM chips disrupting Intel's lock on the data center haven't translated into major threats to Xeons yet. AMD's own effort to produce ARM cores that were socket-compatible with its x86 CPUs, called Project Skybridge, never produced a shipping product, and the company abandoned it in 2015. The last update to AMD's data center roadmap promised the high-performance K12 ARM core for this year, too, but we haven't heard a peep of it since. Despite those various pretenders to the throne, x86 remains the dominant instruction set in the data center, and Xeons are its avatar.

This year might be different. AMD now has a unique arrow in its quiver that other companies don't: a competitive high-performance x86 architecture. Zen has proven a capable and energy-efficient performer in our tests of AMD's Ryzen desktop CPUs, and now the company is taking the fight to Intel in the data center with its Epyc CPU lineup. We already covered some details of this potential resurgence in our preview of the Naples platform. Today, AMD is revealing its chip lineups for two-socket and single-socket servers, as well as some projections of those chips' performance relative to Intel's Broadwell Xeons.

The starting lineup
To build each Epyc package, AMD uses four eight-core modules connected using its Infinity Fabric interconnect. That gives Epyc CPUs a maximum of 32 cores and 64 threads per socket, eight memory channels to DDR4-2666 ECC RAM per socket, and 128 lanes of PCIe 3.0 in total.

Not every server needs that much horsepower, of course, so AMD has sliced and diced that basic package into a variety of products designed to serve prices ranging from $400 and up to $4000 and up. All Epyc CPUs will offer the same memory and PCIe provisions, and some will offer configurable TDPs for more flexibility in system design.

AMD will also offer a subset of Epyc CPUs designed for one-socket servers only. Just like their two-socket relatives, Epyc single-socket CPUs will offer 128 lanes of PCIe 3.0 and eight memory channels. Single-socket operation is the only restriction for these chips, and they'll be available for prices from $700 and up to $2000 and up.

Zen dresses up for business
Although the fundamental Zen core in Epyc is basically the same as that found in desktop Ryzen chips, some of its features are more important for server-class workloads than they are for clients.

The first of these is a virtualized APIC, or Advanced Programmable Interrupt Controller. AMD says this feature helps servers running VMs reduce world switch latency (the state change involved when a system switches from executing guest applications to hypervisor operations) by 50% compared to the Bulldozer architecture and its derivatives.

Epyc CPUs will also make extensive use of the AMD Secure Processor, a dedicated microcontroller embedded on the chip. This chip creates a secure environment that can be used to perform useful features like hardware-validated boot, cryptographic key generation, and key management.

The Secure Processor's key-generation and key-management capabilities will be useful in implementing a feature AMD calls Secure Memory Encryption. Operating systems and hypervisors can request a key from the SP to encrypt sensitive pages, protecting data in flight from being intercepted through attacks on physical memory.

Epyc CPUs will also offer a feature called Secure Encrypted Virtualization that will isolate data owned by hypervisors, virtual machines, and containerized applications from access by other guest environments on a system. With such an arrangement, an attacker in one guest environment wouldn't be able to read data in memory owned and encrypted by another guest, for example. Epyc CPUs will also offer hardware acceleration for the SHA-1 and SHA-256 hashing algorithms.