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Exploring a 333MHz bus for the Athlon XP

The bits on the bus go up and down, up and down...
— 12:00 AM on July 31, 2002

FOR QUITE A WHILE, AMD's Athlon was the fastest x86 processor available. Intel ran into trouble scaling the Pentium III past 1GHz, and the Pentium 4 languished on a 0.18 micron process, with its longer pipeline and lower instructions per clock. In this environment, the Athlon flourished for a lot longer than Intel would have liked.

Since then, the tide has turned. Intel's Northwood Pentium 4, with its 0.13-micron process technology (and resultant sky-high clock speeds), 512KB L2 cache, and 533MHz bus, has come on and come on strong: it's at 2.53GHz and counting, with rumors of 3GHz before the year is out. The Athlon is still a strong player if you factor in price-performance ratio, but the Pentium 4 is king of the hill, and as time goes on, the Athlon is fading.

AMD, meanwhile, is betting that its upcoming Hammer chips will turn things around. But, stray rumors aside, all indications are that the first Hammer won't be ready until December of this year at the earliest. What's AMD to do in the meantime? One answer is Barton, the planned next revision of the Athlon with 512KB of L2 cache. Another possibility, however—and one that's been getting more and more attention recently—is the possibility of a 333MHz bus for the Athlon XP.

It's certainly a move we would understand. Our fingers have repetitive strain injury from typing phrases like "Here we see that the Athlon, with its 266MHz bus, can't take advantage of DDR333's higher memory bandwidth." Indeed, it seems like a no-brainer: Get with the chipset makers to make sure the proper dividers are in place, change the multipliers on some T-breds, and go for it. Unfortunately, it's not quite as simple as that. In this article, we'll explore the possible hurdles that a move to a 333MHz bus would present for AMD, as well as what the Athlon XP might stand to gain from such a move.

A refresher course
Once upon a time a computer's processor and the rest of the system all ran at the same speed. And it was good. But eventually, it got difficult to produce RAM and other components that could keep up with the processor. To get around this problem, it was decided that the processor would run at some multiple of the rest of the system. As far as I know, the first implementation of the concept was Intel's 486/50 DX2, a processor which ran at 50MHz while the rest of the system ran at 25MHz (thus a multiplier of 2X). As time went on, processors ratcheted up in speed regularly, while the speed of the rest of the system (i.e. the "system bus speed") has only changed a few times. The end result is that processor multipliers have climbed steadily higher over time.

While the multiplier concept has allowed processor speeds to scale to extremely high speeds relative to the system bus, there is a downside. Let's take the example of a 1.33GHz Athlon. This chip runs on a 133MHz system bus, and has a multiplier of 10X (10 times 133MHz = 1330MHz or 1.33GHz). This means that the processor can only access other portions of the system on every tenth clock cycle. If the CPU has to store or retrieve data from another part of the system (typically main memory), it might spend several clock cycles spinning its wheels until it hits a clock cycle where it can talk to the rest of the system.

If you're new to all this, you might be scratching your head at the 133MHz bus references; wasn't I just talking about a 266MHz bus? Good catch, grasshopper. The Athlon uses a bus which transfers data on the rising and falling edges of the clock. Thus, a bus with a 133MHz clock speed effectively becomes a 266MHz bus. (This is the same principle used in DDR memory. The Pentium 4 goes a step further, transmitting data four times per clock cycle.)

Setting that aside for a moment, you might speculate that the higher the CPU multiplier is, the more potential for a chip to get stuck doing nothing until the next time it can access some other part of the system. Such a trend would eventually lead to diminishing returns as multipliers rise, because the chip spends too much time waiting on a slow system bus. This is exactly what we're seeing with the Athlon XP. To follow the concept a little bit further, we'd like to get the multiplier back down while keeping the processor speed more or less constant. How can we do that? By raising the speed of the system bus, of course.

Recently, we've seen the release of Athlon chipsets which support memory running at 166MHz DDR, or 333MHz. Unfortunately, the benchmarks have shown that, because the front-side bus is running at an effective 266MHz, the Athlon XP can't currently take very good advantage of the faster memory. The memory is actually running faster than the processor can get to it. Though there are other areas of the system that can benefit from the increased memory bandwidth (see our KT333 article here for more information), these other factors usually have a minimal impact on performance. What would be nice, obviously, is to be able to run the system bus at the same speed as the RAM, to give the processor a wider pipe to main memory. Thus the idea of a 333MHz bus is born.