How has AMD's Athlon 64 delay affected Chaintech's K8 motherboard plans? What has Chaintech done to tame NVIDIA's GeForce FX? How many tasty new features have been revealed in new product roadmaps Chaintech, Intel, SiS, and VIA? Let's find out.
Chipset roadmap updates
In addition to presenting its own products, Chaintech also had some folks from AMD, Intel, NVIDIA, and VIA on hand to discuss their own future products. Much of the information presented wasn't anything radically different than what's already been officially released or unofficially speculated, but here's where the Pentium 4 and Hammer core logic chipset roadmaps stand as of now.
Springdale and Canterwood chipsets both use the new ICH5, but the two have different MCH north bridge chips. The Springdale-PE chipset is a mainstream offering that will support Intel's new 800MHz front-side bus and single-channel DDR400 memory. Canterwood is aimed at the high-end performance market and adds support for dual-channel DDR400 ECC memory, AGP 8X, and a new "Turbo" system timing mode to augment the 800MHz front-side bus.
With the Athlon 64 pushed back to September, it's uncertain what will happen to the chipsets listed on SiS's Hammer north bridge roadmap, which currently lists the SiS 755 Athlon 64 chipset as being mass produced this month. The only other Hammer chipsets on the roadmap are targeted at mainstream and value markets. These chipsets feature integrated graphics, so they're not likely to attract much attention from enthusiasts.
Perhaps the most scandalous element of SiS's chipset roadmaps was in its plans for Pentium 4 north bridge chips. SiS's Pentium 4 north bridge roadmap goes all the way to Q3 2003, but none of the chipsets listed support Intel's upcoming 800MHz front-side bus. Even the SiS 656, which should support dual-channel DDRII-533 memory, only showed as supporting a 533MHz front-side bus. Closer to production is the SiS 655FX, which will sample in May with dual-channel DDR400 support, but again with only a 533MHz front-side bus. Hyper-Threading support is in, just not the new front-side bus speed.
The 533MHz front-side bus listed for the 655FX and 656 chipsets did appear with an asterisk, but what exactly the asterisk means wasn't explained. No one from SiS was available for comment at the event, either. At least for now, it looks like Intel is holding its new technology licenses close to its chest, and SiS may get shafted.
For Hammer, VIA currently has the K8T400, K8T400M, and K8M400. As far as the roadmap is concerned, the only difference between the K8T400 and K8T400M is that the "M" version of the chip is pin-compatible with the K8M400, while the K8T400 is not. All three north bridge chips have a full HyperTransport implementation, 8X V-Link, and an 8X AGP controller. The K8M400 features a new "Castle Rock II" integrated graphics core with a 2x2 rendering pipeline, maximum 64MB frame buffer, and a full MPEG2 decoder. Interestingly enough, the K8M400 will be built on a 0.15-manufacturing process, and its graphics core appears to have at least some multimonitor functionality through "DuoView."
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