As you know, AMD's Athlon 64 didn't quite make it out the door. It's pushed back until this fall while AMD works out some manufacturing snags. But Intel appears to be right on schedule. Just over a week ago, a Canterwood sample platform arrived at Damage Labs, ready for testing. Naturally, we rounded up every competitor we could and put Canterwood through its paces. We've also thrown in AMD's latest and greatest, the Athlon XP 3000+, to see how it measures up to Intel's latest. Read on to see what we found.
Introducing the 875P chipset
Now that it's hitting the market, Canterwood gets a "real" name: the Intel 875P chipset. The 875P is the first of a new wave of chipsets coming from Intel, most of which are currently nestled under the code name Springdale. The 875P brings a whole range of enhancements to the Pentium 4 platform, so I'd better bust out the bullet points to be sure I cover them all. They are...
What Intel is doing, in fact, is "binning" its chips, just like it does its processors. Here's my best guess about what's happening. In all likelihood, the 875P silicon will come from the same wafers and essentially be the same chips as Intel's upcoming Springdale chipset, but Springdale will be a cheaper, higher-volume product. (Springdale chipsets will differ from the 875P only in that they won't include PAT or support for ECC memory types.) The 875P will cost a little more, and will be aimed at workstation users and enthusiasts. Intel probably plans to pick the very fastest Canterwood/Springdale MCH (north bridge) chips and test them to verify they're capable of running with PAT enabled. The best of those chips will be sold as 875P MCH chips.
With PAT enabled, the 875P memory controller will perform some internal memory handling tasks faster, yielding a one-clock improvement in the time for a CPU request to perform memory access and another one-clock improvement in the DRAM chip select process. The total improvementcount with me hereis two clocks for each chip select (CS) process. CS happens at the beginning of a typical memory access, so cutting the CS process by two cycles could lead to real-world reductions in memory access latency.
(It's as if Intel were gearing up to fight a processor with an on-chip memory controller or something, innit?)
Intel emphasizes that 875P chipsets are tested rigorously, at full operating speed, for their ability to run with PAT enabled, so Canterwood motherboards ought to be plenty stable under normal operating conditions. Intel is also quick to point out that PAT happens internally in the memory controller, while external memory interfaces run according to their specifications.
To underline the point that Canterwood is targeting us PC enthusiasts, Intel is making a special version of the ICH5 chip, the ICH5R, with Serial ATA RAID capability. Near as I can tell, this Intel test board will only support RAID 0, or striping, for increased performance. Intel's literature doesn't talk about the possibility of using RAID 1, which would be my preferred config. But then I'm an old fogey. You can read up on all the common RAID levels and their benefits in Diss's impressive ATA RAID round-up.
This decision is kind of curious. Intel's competitors have north-to-south bridge interconnects capable of anywhere from 533MB/s to 1GB/s, but the mighty Canterwood may strain under heavy I/O loads.
Taken together, these new features add up to a much more potent Pentium 4 platform, especially because of the extra bandwidth afforded by the new front-side bus, dual memory channels, and the AGP bus. The P4 has long excelled at streaming media and I/O tasks, and the 875P looks to throw that trend into overdrive.
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