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Yonah promises big things
Undoubtedly the most interesting of Intel's first 65nm processors is Yonah, the first dual-core version of the Pentium M, that will be part of the Napa platform due in early 2006. Yonah is essentially a waypoint between the current Pentium M architecture and Intel's future, common microarchitecture, so it's worthy of some extra attention. Fortunately, Intel's Mooly Eden hosted an IDF session outlining the features of Yonah and the Napa platform, so we have a good picture of how these products should look.

At the heart of Yonah is a tweaked version of the Pentium M microarchitecture that's done so well for Intel over the past few years. If you're not familiar with the Pentium M and how it draws its heritage from earlier Pentium processors, I suggest reading my article about the Pentium M on the desktop, especially the bits about the Dothan core found in many of today's new laptops. Yonah builds on this foundation but follows Intel's company-wide move to dual-core designs.

Yonah is not, however, simply two Pentium M processors located side by side on a single chip or package; it's a truly intentional dual-core design. The two cores on the processor share a bus internal to the chip, behind which sits 2MB of L2 cache that's shared between the cores. (As with Dothan, the L2 cache is 8-way set associative.) This shared cache arrangement should be more efficient than the separate L2 caches on the Smithfield desktop chip, and in mobile apps, efficiency is especially important.

In order to achieve a power envelope similar to that of Dothan with a dual-core processor, Intel's chip designers had to employ a range of power-saving tricks. One of the more interesting of those tricks has to do with that shared L2 cache.

Yonah's Dynamic Smart Cache Sizing illustrated (Source: Intel)

During periods when the CPU isn't busy or there's little demand for cache memory, the contents of Yonah's L2 cache are automatically flushed to memory in stages, saving the power required to keep the cache active. Should the entire contents of the L2 cache be emptied, Yonah can shut off the entire L2 cache, enabling what Intel calls a "deeper sleep" C-state. This facility should save power when the CPU is idle or nearly so.

One of Dothan's few performance weaknesses is in applications that use lots of vector math, such as video encoding programs that use SSE instructions. Compared to the Pentium 4 and Athlon 64, the Pentium M sometimes looks a little pokey at such tasks. Yonah should change all that, not just because of the addition of a second CPU core, but because of added capabilities in each core.

As you may know, modern x86 CPUs combine a RISC-like processor core with decoders for the x86 instruction set's more complex, CISC-style instructions. These decoders translate x86 instructions into simpler instructions (Intel calls them micro-ops) that can run natively on the RISC-like core behind them. The rate at which the processor decodes x86 instructions is one of the potential bottlenecks of such a design, and it has been something of a problem for the Pentium M. Yonah distinguishes itself from past Pentium Ms because all three decoders can now handle 128-bit SSE2 instructions, allowing the CPU to dispatch more of these instructions per clock.

The Pentium M architecture also boosts its performance through a capability Intel has dubbed micro-ops fusion. When an x86 instruction is decoded into two micro-ops that are closely related, the Pentium M's decoders can sometimes fuse them together and send them down the execution pipeline as one micro-op for more efficient execution. Yonah extends micro-ops fusion to SSE instructions, a move Intel claims makes for better use of the chip's execution resources and decoder bandwidth.

The enhancements to instruction decoding and grouping should help quite a bit with the Pentium M's vector math performance, but that's not all. Yonah also supports SSE3, with instructions intended to accelerate complex arithmetic, video encoding, and vertex processing for graphics. At the execution level, Intel says Yonah is up to 30% faster at SSE2's Shuffle and Unpack instructions, and the integer DIV instruction is quicker, too. The chip also includes a new register that offers control over rounding of floating-point numbers, more write output buffers, and the nearly ubiquitous "enhanced data pre-fetch" that we've come to know and love with every new chip generation. All told, each of Yonah's cores packs quite a few enhancements aimed at the acceleration of vector math, and especially at the handling of digital media encoding and decoding.

The end result should be a processor much better suited for multimedia playback—and a processor with a performance balance even more acceptable for use in desktop and server-class applications. In fact, Intel won't wait for its next-generation common microarchitecture to pull Yonah into its desktop and workstation/server lineups. Systems bearing Intel's new Viiv brand for digital home entertainment must include a dual-core processor, and Yonah is an option alongside the Pentium D and Extreme Edition. I'd expect to see Viiv-branded Yonah-based desktops and media center PCs early in '06. There will also be a Yonah-derived product, currently code-named Sossaman, pitched as a lower-power option for data centers.

Yonah should more or less hold the line on power, with levels similar to Dothan's, by taking advantage of a number of advances. Parallelism is a big one, as the past year has proven. The move to dual cores will allow Yonah to deliver better performance at roughly the same clock speeds as Dothan, with no need to seek higher speeds. The die shrink to 65nm will help, too, of course, as will dynamic cache sizing and the deeper sleep state. The improvements in vector math performance may lead to higher peak power consumption, but Intel has claimed in the past that micro-ops fusion is advantageous because less energy is consumed per instruction sequence. Yonah may be able to realize similar benefits from its extension of micro-ops fusion and other per-clock performance increases.

Napa: Intel's next Centrino platform
There's more to the Napa platform than just Yonah, of course. The core-logic chipset, code-named Calistoga, will be a mobile version of the 945 Express chipset. There's also an Intel wireless networking solution in the mix, although we won't talk much about that.

The Mobile 945 Express chipset will support bus speeds up to 667MHz, which gives us a very good clue about Yonah's likely front-side bus speed. The chipset also packs a range of power-saving features of its own. Among them is an automatic display brightness control that raises and lowers the intensity of LCD backlighting in response to changes in ambient light. Intel says the operation of this mechanism should be imperceptible to the user.

Additionally, Napa will set a new baseline for Intel mobile graphics with the inclusion of the Graphics Media Accelerator 950 integrated graphics core running at 250MHz. This DirectX 9-class graphics engine should be capable of supporting the Aeroglass look in Windows Vista, and it can accelerate MPEG2 processing in hardware, among other things.