Exploring the performance impact of memory latency

Lower latencies are a good thing, of course, but how much can they really improve system performance? Are exotic, low-latency DIMMs worth the price premium? Read on as we explore the effects of memory latency on Athlon 64 performance in synthetic memory benchmarks, games, and real-world applications.

Memory latency?
Before diving into our benchmark results, it's worth taking a moment to go over how memory access works and where the various latencies come into play. Memory is organized like a spreadsheet, with data stored in cells that can be identified by a corresponding column and row. Spreadsheets can also be made up of multiple sheets, and similarly, memory can be made up of multiple banks. If we want to access a specific cell of memory, the system must first activate the sheet, or bank, containing the desired row. Next, the system sends an active command to the desired row. Once the row is activated, the system can issue read or write commands to specific columns in the row. When reading or writing has been completed, a precharge command is sent to close the row.

There are delays between each of the steps in memory access. These delays are referred to as latencies and expressed as a number of clock cycles. Here's a brief explanation of some of the most common, and important, memory timing parameters that affect access latencies:

• RAS-to-CAS delay (tRCD) — The RAS-to-CAS delay occurs between the time a row is activated and when the first read or write operation is performed.

• CAS latency (CL) — CAS latency refers to the delay between when a read operation is issued and when the data returned by that read is considered valid.

• RAS precharge (tRP) — The RAS precharge is the delay between when a precharge command is issued to close a row and when the next active command can be issued.

• Active-to-precharge delay (tRAS) — This latency actually spans several steps in the memory access process. The active-to-precharge delay refers to the minimum number of cycles that must elapse between an active and precharge command.

Of course, no discussion of memory latency would be complete without mentioning the DRAM command rate. The command rate is the delay between when a memory chip is selected and when the first active command can be issued. The factors that determine whether a memory subsystem can tolerate a 1T command rate are many, including the number of memory banks, the number of DIMMs present, and the quality of the DIMMs. Some memory manufacturers claim that their DIMMs are rated for operation with a one-cycle (1T) command rate.

Since latencies refer to delays, lower is better. That doesn't mean you should hop into your motherboard's BIOS and set each memory timing option to its lowest possible value, though. Memory modules are rated for a specific set of latencies at a given clock speed, and they're generally not stable with lower latencies. A DIMM's latencies are usually expressed as a series of four hyphenated numbers corresponding to the CAS latency, RAS-to-CAS delay, RAS precharge, and active-to-precharge delay. Low latency DDR400, for example, is generally rated for 2-2-2-5 timings at 400MHz. That refers to two cycles of CAS latency, RAS-to-CAS delay, and RAS precharge, and five cycles of active-to-precharge delay.