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puppetworx wrote:

PCPer noted an issue with Ryzen yesterday and speculated power delivery was at fault. AMD says a fix is on the way.

Perhaps there are more power delivery gremlins which the high performance plan 'resolves'.

This might be the first time I've ever heard of overclocking a system to achieve stability not possible at stock.

just brew it! wrote:

The descriptions/diagrams I've seen of the architecture indicate that the 8MB L3 per CCX is in 4 2MB chunks, with lowest latency being to the core "closest" to it.

Not that this refutes what you've seen, but in a 2+2 config, CPU-Z still sees all 16MB of L3 cache. Some of it might come at a higher latency penalty, I suppose.

derFunkenstein wrote:

just brew it! wrote:

The descriptions/diagrams I've seen of the architecture indicate that the 8MB L3 per CCX is in 4 2MB chunks, with lowest latency being to the core "closest" to it.

Not that this refutes what you've seen, but in a 2+2 config, CPU-Z still sees all 16MB of L3 cache. Some of it might come at a higher latency penalty, I suppose.

Yeah, that's my understanding. And the situation may be different if those cores are disabled at the factory.

just brew it! wrote:

Yeah, that's my understanding. And the situation may be different if those cores are disabled at the factory.

I wonder if it will be like the Phenom II X2 555, built one of those for a budget machine with an hd5770 and unlocked to a quad, never had any issues.

I think AMD wisened up to that. You don't see dormant cores/modules in six- or four-core FX processors getting unlocked, at least not that I've heard of.

But yeah I totally had Phenom II X2 550 that unlocked to "Phenom II X4 B50" according to the BIOS. Those were the good old days.

DancinJack wrote:

Aranarth wrote:

I was really hoping that r5 would be a single ccx not two 1/2 ccx's (2x2) put together.
This was why I was saying that I expect r5's to clock better than 3x3 or 4x4.

Even if they did have only one CCX, they weren't going to clock much, if any, better than the 8 core parts! You guys keep saying this stuff as if it's all about the TDP and we're butting up against a thermal headroom wall. That's not it. The default voltage for these parts is ~1.36 IIRC. You're just not going to get much headroom out of a chip that starts that high.

I am thinking the OC headroom or lack thereof is more on GF than AMD.

Vhalidictes wrote:

I do think that 3+3 is probably fine, though, depending on the above... although again 4+2 might allow for additional die harvesting.

I'm sure it's just die harvesting, and they need to harvest according to the same criteria as Anandtech says. Otherwise that "additional" die they harvested with a different configuration will have performance implications, and that's probably not something the PC world is ready for (though they can get away with something similar in mobileland with the dual-sourcing like with iPhone 6s CPU/Iphone 7 modem).

Glorious wrote:

Vhalidictes wrote:

I do think that 3+3 is probably fine, though, depending on the above... although again 4+2 might allow for additional die harvesting.

I'm sure it's just die harvesting, and they need to harvest according to the same criteria as Anandtech says. Otherwise that "additional" die they harvested with a different configuration will have performance implications, and that's probably not something the PC world is ready for (though they can get away with something similar in mobileland with the dual-sourcing like with iPhone 6s CPU/Iphone 7 modem).

Or they could give them a slightly different model number. 3+3 = 1600. 4+2 = 1605 or 1600c ?