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chuckula
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Here's what a real 10nm process looks like (literally)

Tue Mar 28, 2017 8:44 pm

Jeff Kampman's twitter feed has some good links to some resources in Intel's Technology and Manufacturing Day

There are some videos & slide decks available there, but by far the coolest one I've seen is their presentation regarding some very specific features about Intel's 10nm process, which is debuting later this year and has quite a few differences from other lithographic processes that are referred to as "10nm".

There's a lot of cool information in that slide deck, but my favorite part is on slides 9 & 10 where they have scanning electron microscope images of different transistor sizes from the first finfet parts at 22nm all the way down to 10nm. I really like that because plenty of companies love to say 10nm, but Intel shows you what they mean by 10nm.

Other cool stuff about Intel's 10nm node shrink is that they have added two new tweaks to their transistor layout that increase the transistor density but don't rely on the standard lithographic die-shrink techniques (although those are present too). First is a rearrangement of the metal contact between the transistor and the metallization layer (see slide 15). In the past the metal contact was to the side of the gates on the transistor, but now the metal contact is directly "over" (or maybe under?) the active gate, which reduces the overall footprint of the transistor. The second improvement is to reduce the number of "dummy" gate structures that were etched in the wafer to protect the "active" gates that actually operate to switch the transistor (slide 16). In Intel's prior designs it looks like two of these dummies were used on the sides of a transistor, but at 10nm Intel has reduced this down to a single dummy.

The contact over active gate and single dummy gate techniques got a buzzy marketing name of "Hyperscaling" because they increase transistor density in ways that go beyond the usual effects of a die-shrink. I'm usually not a big fan of marketing buzzwords, but when Intel gins up a marketing name to describe low-level transistor structural features, you know that they are pretty excited about what they've been able to accomplish.
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Captain Ned
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Re: Here's what a real 10nm process looks like (literally)

Tue Mar 28, 2017 8:50 pm

Yikes. Over 100 million transistors per square millimeter.
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Re: Here's what a real 10nm process looks like (literally)

Tue Mar 28, 2017 9:03 pm

Captain Ned wrote:
Yikes. Over 100 million transistors per square millimeter.

Yikes indeed. The first transistors I dealt with looked like these. We're talking cubic millimeters per transistor. :lol:
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chuckula
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Re: Here's what a real 10nm process looks like (literally)

Tue Mar 28, 2017 9:06 pm

just brew it! wrote:
Captain Ned wrote:
Yikes. Over 100 million transistors per square millimeter.

Yikes indeed. The first transistors I dealt with looked like these. We're talking cubic millimeters per transistor. :lol:


I'd still take one of those any day if I need a high-power solid-state switch :-)
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Re: Here's what a real 10nm process looks like (literally)

Tue Mar 28, 2017 9:09 pm

just brew it! wrote:
Captain Ned wrote:
Yikes. Over 100 million transistors per square millimeter.
Yikes indeed. The first transistors I dealt with looked like these. We're talking cubic millimeters per transistor. :lol:

Why do I think that chip layout just got a whole lot more difficult? Dear Bob, just how many layers will be needed in that silicon to connect & feed all those transistors.
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Re: Here's what a real 10nm process looks like (literally)

Tue Mar 28, 2017 9:10 pm

chuckula wrote:
I'd still take one of those any day if I need a high-power solid-state switch :-)

Found in most every solid-state audio power amp ever, except for the bizarro designs.
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Re: Here's what a real 10nm process looks like (literally)

Tue Mar 28, 2017 9:18 pm

Captain Ned wrote:
chuckula wrote:
I'd still take one of those any day if I need a high-power solid-state switch :-)

Found in most every solid-state audio power amp ever, except for the bizarro designs.

...and modern versions (in surface-mount epoxy encapsulated packages instead of metal cans) are in every modern motherboard's VRM section.

Well OK, modern VRMs use MOSFETs instead of BJTs, but they're of comparable size. (BJTs amplify current, whereas MOSFETs modulate their resistance based on an applied control voltage. Either can be used as a solid-state switch, the circuit designs are just a little different...)
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Vhalidictes
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Re: Here's what a real 10nm process looks like (literally)

Wed Mar 29, 2017 3:04 pm

Captain Ned wrote:
Yikes. Over 100 million transistors per square millimeter.


It's going to be interesting to see how Intel plans on cooling CPU hot-spots with such a dense chip. The heat transfer capability of current 14nm CPUs isn't great.
 
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Re: Here's what a real 10nm process looks like (literally)

Wed Mar 29, 2017 3:34 pm

Vhalidictes wrote:
Captain Ned wrote:
Yikes. Over 100 million transistors per square millimeter.

It's going to be interesting to see how Intel plans on cooling CPU hot-spots with such a dense chip. The heat transfer capability of current 14nm CPUs isn't great.

They could probably improveme things significantly by grinding down the backs of the dies before packaging the CPUs. This "back grinding" is typically done only for specialized devices (e.g. mobile SoCs which will be used in a "stacked" configuration due to space constraints or high-density DRAM chips using multiple dies connected with TSVs), but I see no reason it couldn't be applied to regular CPUs.

A little background...

The thickness of the silicon die depends on the diameter of the original wafer. The larger the wafer the thicker the die, because larger wafers need to be thicker to give them sufficient mechanical strength to resist breakage during wafer processing (before the wafer is cut apart into individual dies). So as fabs have moved to larger and larger wafers, the thickness of the chips has also increased.

Why does this matter? Well, the thermal conductivity of silicon basically sucks compared to most metals (less than half that of copper), and the active circuitry (where the heat gets generated) is on the underside of the die, opposite from the thermal interface. So as wafers have gotten larger (and therefore thicker), the heat has to pass through a thicker layer of silicon before it gets to the IHS, in turn creating a larger temperature gradient between the bottom and top of the chip, and reducing the ability to get rid of that heat without cooking the increasingly sensitive (due to smaller feature size) circuitry.
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chuckula
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Re: Here's what a real 10nm process looks like (literally)

Wed Mar 29, 2017 3:38 pm

just brew it! wrote:
Vhalidictes wrote:
Captain Ned wrote:
Yikes. Over 100 million transistors per square millimeter.

It's going to be interesting to see how Intel plans on cooling CPU hot-spots with such a dense chip. The heat transfer capability of current 14nm CPUs isn't great.

They could probably improveme things significantly by grinding down the backs of the dies before packaging the CPUs. This "back grinding" is typically done only for specialized devices (e.g. mobile SoCs which will be used in a "stacked" configuration due to space constraints or high-density DRAM chips using multiple dies connected with TSVs), but I see no reason it couldn't be applied to regular CPUs.

A little background...

The thickness of the silicon die depends on the diameter of the original wafer. The larger the wafer the thicker the die, because larger wafers need to be thicker to give them sufficient mechanical strength to resist breakage during wafer processing (before the wafer is cut apart into individual dies). So as fabs have moved to larger and larger wafers, the thickness of the chips has also increased.

Why does this matter? Well, the thermal conductivity of silicon basically sucks compared to most metals (less than half that of copper), and the active circuitry (where the heat gets generated) is on the underside of the die, opposite from the thermal interface. So as wafers have gotten larger (and therefore thicker), the heat has to pass through a thicker layer of silicon before it gets to the IHS, in turn creating a larger temperature gradient between the bottom and top of the chip, and reducing the ability to get rid of that heat without cooking the increasingly sensitive (due to smaller feature size) circuitry.


That's an excellent point. Modern packaging using the "flip chip" configuration puts all the heat producing parts of the chip on the opposite side of the heat sink interface, so grinding the chip to cut out unneeded silicon is one way to improve cooling. There are certainly more exotic ways to do it including microfluidic channels with inert liquid coolant, but grinding the chip down sounds a lot easier to do.
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Re: Here's what a real 10nm process looks like (literally)

Wed Mar 29, 2017 4:00 pm

chuckula wrote:
That's an excellent point. Modern packaging using the "flip chip" configuration puts all the heat producing parts of the chip on the opposite side of the heat sink interface, so grinding the chip to cut out unneeded silicon is one way to improve cooling. There are certainly more exotic ways to do it including microfluidic channels with inert liquid coolant, but grinding the chip down sounds a lot easier to do.

Yeah, and since they're already doing it for other types of chips, there's no need to develop any new tech. All the equipment and processes they need to do it already exist.
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Re: Here's what a real 10nm process looks like (literally)

Thu Mar 30, 2017 4:31 am

Interesting to see the future in CPU!
But after looking at the forums at Techreport and Anadtech I noticed that most people are interested in overclocking. It should be harder with 10 nm or even worse at 7 nm. But of course it is better for laptops needing long battery life.
 
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Re: Here's what a real 10nm process looks like (literally)

Thu Mar 30, 2017 7:19 am

just brew it! wrote:
Vhalidictes wrote:
Captain Ned wrote:
Yikes. Over 100 million transistors per square millimeter.

It's going to be interesting to see how Intel plans on cooling CPU hot-spots with such a dense chip. The heat transfer capability of current 14nm CPUs isn't great.

They could probably improveme things significantly by grinding down the backs of the dies before packaging the CPUs. This "back grinding" is typically done only for specialized devices (e.g. mobile SoCs which will be used in a "stacked" configuration due to space constraints or high-density DRAM chips using multiple dies connected with TSVs), but I see no reason it couldn't be applied to regular CPUs.

A little background.


Thats neat! I guess anything to improve the ability to keep these things cool becomes worth it as things get smaller.

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