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chuckula
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Skylake X: Bye Bye Rings, Hello Mesh

Fri Jun 16, 2017 7:00 am

This isn't exactly a surprise but Intel has released some additional tidbits on the on-die mesh interconnect that is replacing the venerable ring bus for core to core communication in Skylake X.

Intel has a blog post about it and PC perspective has an interesting article too.

In brief, instead of sending a data packet through a ring with a potential hop between rings if needed on the largest Haswell/Broadwell chips, the mesh sends data first "vertically" in one direction along rows of cores until the packet hits the right row and then "horizontally" across columns until the packet reaches the correct destination. That destination could be another core but it could also be a memory controller, I/O, or even an IGP in future products with on die graphics.

The most interesting part is that this isn't Intel's first mesh. That distinction goes to Knights Landing where up to 72 cores are connected together with a mesh. So if KNL hits 72 cores, it looks like there is room to scale this interconnect.
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Fri Jun 16, 2017 9:28 am

chuckula wrote:
The most interesting part is that this isn't Intel's first mesh. That distinction goes to Knights Landing where up to 72 cores are connected together with a mesh. So if KNL hits 72 cores, it looks like there is room to scale this interconnect.


KNL has cores organised in "tiles" of 2 cores, meaning it only has 36 nodes on the mesh.
 
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Fri Jun 16, 2017 9:50 am

The more we advance, the more nuanced process layout and memory access have to be.

That said, it probably won't make much difference for consumers. Intel could easily "tile" 4+ cores into a node without much engineering if they've already done 2. They generally aren't so shortsighted to design a new structure without thinking about the next few iterations.
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Fri Jun 16, 2017 9:54 am

Waco wrote:
The more we advance, the more nuanced process layout and memory access have to be.

That said, it probably won't make much difference for consumers. Intel could easily "tile" 4+ cores into a node without much engineering if they've already done 2. They generally aren't so shortsighted to design a new structure without thinking about the next few iterations.


Yeah, even for 16 cores near the very high end of the "consumer" space it wouldn't make a huge difference, especially when most consumer workloads aren't that obsessed with inter-core communication. Of course, Skylake X is just a rebranded Xeon, and there are workloads where those chips need to care about inter-core communication and be able to scale to higher core counts without choking.
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Fri Jun 16, 2017 9:57 am

Any smart gerbils have an idea on how this compares to AMD's Infinity Fabric?
 
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Fri Jun 16, 2017 10:07 am

Losergamer04 wrote:
Any smart gerbils have an idea on how this compares to AMD's Infinity Fabric?


AMD hasn't released a huge amount of information about Infinity Fabric but there are some pretty fundamental differences based on what we already know about RyZen.

First, Infinity Fabric, at least as it exists today, is fundamentally tied to the memory controller in each RyZen chip while this mesh interconnect can (theoretically) operate completely independently of the memory controller although it connects to the memory controllers in any practical chip. Second, Infinity Fabric is designed from the outset to communicate off-chip with other pieces of silicon. There is nothing inherent with the mesh design that allows for off-chip communication although using a silicon based solution like EMIB it might be possible to extend a mesh network between two chips with relatively low latency.
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Fri Jun 16, 2017 11:19 am

Working with HBM coupling to CPU and GPU has probably given AMD a boost in experience with respect to infinity fabric and memory controllers. My guess is that looming :D on the horizon; both Intel and AMD are converging on the same weave based paradigm.
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Fri Jun 16, 2017 11:37 am

Waco wrote:
Intel could easily "tile" 4+ cores into a node without much engineering if they've already done 2.

Mr Bill wrote:
Working with HBM coupling to CPU and GPU has probably given AMD a boost in experience with respect to infinity fabric and memory controllers. My guess is that looming :D on the horizon; both Intel and AMD are converging on the same weave based paradigm.

If Intel puts four CPUs on a ring, and then weaves the rings together in a mesh... would the result be chainmail? ;)
 
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Fri Jun 16, 2017 11:56 am

UberGerbil wrote:
If Intel puts four CPUs on a ring, and then weaves the rings together in a mesh... would the result be chainmail? ;)

Only if you're using the International pattern (European 1-into-4 if you want to get technical).
 
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Fri Jun 16, 2017 1:05 pm

UberGerbil wrote:
Waco wrote:
Intel could easily "tile" 4+ cores into a node without much engineering if they've already done 2.

Mr Bill wrote:
Working with HBM coupling to CPU and GPU has probably given AMD a boost in experience with respect to infinity fabric and memory controllers. My guess is that looming :D on the horizon; both Intel and AMD are converging on the same weave based paradigm.

If Intel puts four CPUs on a ring, and then weaves the rings together in a mesh... would the result be chainmail? ;)

I think it's basically scale mail, with the cores being the scales.
 
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Fri Jun 16, 2017 1:07 pm

Vhalidictes wrote:
UberGerbil wrote:
If Intel puts four CPUs on a ring, and then weaves the rings together in a mesh... would the result be chainmail? ;)

Only if you're using the International pattern (European 1-into-4 if you want to get technical).
I had to look that up! Its pretty interesting.
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Fri Jun 16, 2017 5:22 pm

One thing is that is being overlooked is that Intel can now to big.LITTLE in the sense that both their larger cores and their smaller cores now have a common on-die fabric. As mentioned in this thread, the Knight's Landing Xeon Phi uses this mesh topology the core's used in Knight's Landing are based upon the Silvermont core design. Of course, this is no indication that they will release something like this (though it would surprise me if they didn't experiment with this internally).

Over looked with this topology change is that this has the potential to reduce power consumption. To move data long the previous ring bus could hit half of the core before reaching its destination, burning power at every step. While some routing logic is necessary for these new chips, the reducing on the number of hops between nodes will ultimately save power.
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Mon Jun 19, 2017 1:35 pm

I wonder if the interposer used in HBM can be used to provide mesh or infinity link between modules in a package.
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Mon Jun 19, 2017 5:59 pm

Mr Bill wrote:
I wonder if the interposer used in HBM can be used to provide mesh or infinity link between modules in a package.


Yes. Raja of AMD has dropped hints that that is the direction he's going for GPUs. Same principles for scaling the number of CPUs cores in a design.

Intel also has their EMIB technology to link multiple dies together. The Stratix 10 part is currently shipping using it.
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Mon Jun 19, 2017 6:24 pm

the wrote:
Mr Bill wrote:
I wonder if the interposer used in HBM can be used to provide mesh or infinity link between modules in a package.


Yes. Raja of AMD has dropped hints that that is the direction he's going for GPUs. Same principles for scaling the number of CPUs cores in a design.

Intel also has their EMIB technology to link multiple dies together. The Stratix 10 part is currently shipping using it.


Not producing GPUs in a socket AM4 package was a missed opportunity. I imagine that producing reliable/cheap multi-socket motherboards is the roadblock there.
 
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Mon Jun 19, 2017 10:38 pm

Raven Ridge will offer a CPU+GPU combo in AM4 packaging. It is due later this year.
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Tue Jun 20, 2017 10:45 am

the wrote:
Raven Ridge will offer a CPU+GPU combo in AM4 packaging. It is due later this year.


I know that APUs are and will continue to be a thing, it's just that having the GPU in its own socket would help with power delivery and heat dissipation, and possibly PCIe lane tracing as well.
 
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Re: Skylake X: Bye Bye Rings, Hello Mesh

Sat Jun 24, 2017 7:51 am

Vhalidictes wrote:
I know that APUs are and will continue to be a thing, it's just that having the GPU in its own socket would help with power delivery and heat dissipation, and possibly PCIe lane tracing as well.

For weaker APU-style GPU, the separate packaging will create issues with PCIe lane tracing and additional wires on the motherboard. For discrete type stronger/bigger GPUs, not sure about power delivery and heat dissipation; how do you channel 200W+ power over the motherboard traces without frying the board itself? Not to mention you need another tower-style heatsink to carry the heat from the socket, unless you are doing watercooling.
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