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chuckula
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Re: The Threadripper: THERE. ARE. FOUR. DIES!

Sat Jul 29, 2017 1:53 pm

Ifalna wrote:
Look again, there are FIVE lights!

*uses torture device*



Picard should have just started picking random numbers to mess with him.
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K-L-Waster
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Re: The Threadripper: THERE. ARE. FOUR. DIES!

Sat Jul 29, 2017 3:35 pm

chuckula wrote:
Ifalna wrote:
Look again, there are FIVE lights!

*uses torture device*



Picard should have just started picking random numbers to mess with him.


"How many lights do you see?"

"37.2"

"You see 0.2 of a light?"

"Don't you?"
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Redocbew
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Re: The Threadripper: THERE. ARE. FOUR. DIES!

Sat Jul 29, 2017 4:00 pm

How many lights do you see?

42!

Hmm... The ultimate answer to life the universe and everything. Well played. You may go.
Do not meddle in the affairs of archers, for they are subtle and you won't hear them coming.
 
freebird
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Re: The Threadripper: THERE. ARE. FOUR. DIES!

Sat Jul 29, 2017 6:14 pm

With Four dies present and being based on pretty near the same socket as EPYC, the question then remains... could they enable 4-cores on each and have 2-dimms per core for 8 channels of memory? Perhaps in the future and enable more cores? Maybe an upgrade next year with Ryzen 2 or 7nm late in 2018? Leaves room for modifications and also many questions...

Hopefully with the bugs worked out with the Agesa 1.0.0.6a release TR can use High Speed DDR4 if not using ECC memory, because my Ryzen 1700 can run my Trident Z 64GB DDR4 3000 CL14 memory with no hiccups at DDR4 3200 CL14-14-14-34 and v1.35 although I did bump the SoC voltage up to 1.2v to make sure it doesn't fluctuate and cause an issue. Prior to the 1.0.0.6a I had to run 2667 CL14 or 2933 to 3200 with a CL of 18
 
Waco
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Re: The Threadripper: THERE. ARE. FOUR. DIES!

Sun Jul 30, 2017 9:42 pm

I wouldn't expect board partners to keep 8 channels of memory quiet...especially since it costs so much more to build a board that way.

That said, I would love to be proven wrong. :) If true, 32-core Epyc chips would drop right in.
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the
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Re: The Threadripper: THERE. ARE. FOUR. DIES!

Sun Jul 30, 2017 9:53 pm

freebird wrote:
With Four dies present and being based on pretty near the same socket as EPYC, the question then remains... could they enable 4-cores on each and have 2-dimms per core for 8 channels of memory? Perhaps in the future and enable more cores? Maybe an upgrade next year with Ryzen 2 or 7nm late in 2018? Leaves room for modifications and also many questions...

Hopefully with the bugs worked out with the Agesa 1.0.0.6a release TR can use High Speed DDR4 if not using ECC memory, because my Ryzen 1700 can run my Trident Z 64GB DDR4 3000 CL14 memory with no hiccups at DDR4 3200 CL14-14-14-34 and v1.35 although I did bump the SoC voltage up to 1.2v to make sure it doesn't fluctuate and cause an issue. Prior to the 1.0.0.6a I had to run 2667 CL14 or 2933 to 3200 with a CL of 18


The problem with this is how pads are allocated on a package. It would have to be the same dies routed to the memory channels if they were failed Epyc parts. The other dies might be enabled but Thread Ripper motherboards won't have all eight channels wired up. Due to this, the other dies would have rely on remote NUMA nodes for memory access, so the performance gains will fall short of a true Epyc system.
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