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Our pal Der8Auer has gotten his hands on one of the big Skylake X parts that are launching later this month and done the needful with a delid to show off the die:



This is the die that is used for the 12 - 18 core end of the Skylake X (and Xeon W) lineup that Intel labels as an "Extreme Core Count" (XCC) die. The only bigger Skylake silicon is for the Xeon Gold/Platinum lineup that goes up to 28 cores.

Given that the package has a long dimension (vertical in that photo) of 52.5 mm and a short dimension of 45 mm, I have done my usual number crunching to come up with a die size estimation of about 491 mm^2 (roughly 21.77mm high and 22.56 mm wide).

I have already estimated the die size of the "small" Skylake X parts at about 327 mm^2 here for comparison.

So, given that the "small" Skylake X scales up to 10 cores the "big" Skylake X with 18 cores occupies a die that is almost exactly 50% larger at 491 mm^2 / 327 mm^2. That's a 50% area scaling for an 80% core count scaling because the uncore area occupies a fixed amount of space across both processors so the larger chips can add additional cores while the total die area increases at a less-than-linear rate.

We'll see how it performs later this month. Early indications are that it is a strong overclocker.

Correction: 12-18 core die is High Core Count (HCC), not XCC.

In Soviet Russia, three letter acronyms define you!

Can you really estimate the die area when the whole area is covered by the "interposer" err exerposer?

Damn. Big.
Intel's AVX and core is big... but, with less integration on die for Ryzen 8C did I expected smaller than this.

I believe both your estimates are a tad high.

The uncore may not be the same. The HCC and XCC dies have Omnipath options available. The Omnipath controller gets its own PCIe 16x link which remain on package. The number of UPI links on-die may also be different too as the LCC silicon is expected to be used only in dual socket boards where as gold/platinum may go up to 8 sockets.

Intel has also indicated that there will be Xeons with on package FPGAs.

That die looks really weird. In fact, it looks like Intel took a already-made Socket 1155 package and glued it onto a Socket 2066 package.

In fact, given the lack of vertical space it does look like a simple interposer. WTH would be the reason for doing that?

Vhalidictes wrote:

That die looks really weird. In fact, it looks like Intel took a already-made Socket 1155 package and glued it onto a Socket 2066 package.

In fact, given the lack of vertical space it does look like a simple interposer.

Yeah, PoP looks weird. Not sure if Intel went this route in order to simplify assembly due to the use of different dies, or if there was some other benefit.

techguy wrote:

Vhalidictes wrote:

That die looks really weird. In fact, it looks like Intel took a already-made Socket 1155 package and glued it onto a Socket 2066 package.

In fact, given the lack of vertical space it does look like a simple interposer.

Yeah, PoP looks weird. Not sure if Intel went this route in order to simplify assembly due to the use of different dies, or if there was some other benefit.

Well, I'd assume that the main difference between packages is that there are two more memory channel pins attached to LGA 2066, but that doesn't make any sense either because any of the pins on the bottom package would have to be on the top one as well; Whatever the top one is, it can't be LGA 1155 in any case.

Which takes us back to your question "WTH advantage besides increasing manufacturing errors does PoP provide?

Possible Answer: Intel changed the socket design sometime after the dies were produced?

Pop makes since as the CPU package is used in three different socket packages so far: LGA 2066 with some PCIe and memory channels disabled, LGA 3467 for vanilla Xeons and LGA 3467 for Xeons with Omnipath. The last option is the real driver for pop packing since the bottom package will host the Omnipath controller chip too. Presumably there will be a fourth socket package that'll leave room for a FPGA at some point it the future.

Using pop, Intel could test the cpu package independent of the Omnipath logic and bin accordingly. Not sure if that'd actually be worth the extra expense by itself but in aggregate with the different packing option this does make some sense.

Edit: I am grammar gooder

the wrote:

Pop makes since as the CPU package is used in three different socket packages so far: LGA 2066 with some PCIe and memory channels, LGA 3467 for vanilla Xeons and LGA 3467 for Xeons with Omnipath. The last option is the real driver for pop packing since the bottom package will host the Omnipath controller chip too. Presumably there will be a fourth socket package that'll leave room for FPGA some point it the future.

Oh, yeah that makes a lot of sense when you put it that way. I'd read that Intel originally wasn't going to offer HCC chips to consumers, so if true then the HCC chips would never have been designed for the LGA-2066 v3 socket and would require an adapter package.

Oddly, if that's the case then it's possible the HCC Xeons may still have solder if they don't require the additional package PCB, as the heatspreader would already be different than the one used above which attaches to both substrates.

Another remote possibility has struck me. There has been a rumor of Intel adopting AMD graphics.. As crazy as it would be, POP packaging would be a cheap and easy way to include both a CPU and GPU in a highend socket. The CPU side wouldn't need to be modified as there are 16 PCIe lanes not exposed to socket LGA 3647 or 2066 that could be used by the GPU. The other interesting factor is who would want such a chip. Hint: it is a fruity company.

the wrote:

Another remote possibility has struck me. There has been a rumor of Intel adopting AMD graphics.. As crazy as it would be, POP packaging would be a cheap and easy way to include both a CPU and GPU in a highend socket. The CPU side wouldn't need to be modified as there are 16 PCIe lanes not exposed to socket LGA 3647 or 2066 that could be used by the GPU. The other interesting factor is who would want such a chip. Hint: it is a fruity company.

?? but what about heat ??

Why would Apple engineers want to put 350-500 W in one socket?

(18C Skylake products released so far have been 140-200 W, Vega products have been 210-350 W, though only most, not all, of that is for the package.)

Topinio wrote:

Why would Apple engineers want to put 350-500 W in one socket?

If Apple wanted they could certainly design a cooling system to handle it in a Mac pro. Odds are Apple would trim the specs or use more expensive, higher grade silicon in order to use lower voltages and reduce heat. I don't know what the point of a Sky-X chip with a combined GPU would be since a workstation would be better off with a full-size card, but it hasn't stopped Apple from doing it in the past.