Personal computing discussed
Moderators: renee, Flying Fox, morphine
Some workloads which are CPU-bound and not memory-bound will perform better when CPUs with more performance come along; some workloads which are memory-bound and not CPU-bound won't. This should be obvious, as should that in workloads which are memory-bound on the socket and whose memory requirements scale with number of threads used, trying to use more threads won't ever help.
Are you arguing that companies (AMD??) should not be designing and producing newer CPUs which will help the first set, because that doesn't help the last set of use cases?
chuckula wrote:True but irrelevant because you are forgetting to factor in scaling to your arguments.
chuckula wrote:Right now there are x% of workloads that are "compute bound" on, let's say, a 32-core CPU with 4 channels of RAM where the RAM doesn't really matter. So we can just scale that up right!
chuckula wrote:Well, your next CPU is now only running (x- Δ)% of workloads in your "compute bound" scenario and a brand new set of Δ workloads suddenly aren't feeling the love from all those extra cores. And Δ is not an insignificant number.
chuckula wrote:I'm sure we'll see this to different degrees when Threadripper2 and Skylake X2 launch later this year with reduced memory I/O levels compared to their server equivalents. Sure it won't affect Cinebench but there will be repercussions.
chuckula wrote:On a slightly more serious note. Can't a particular core timeshare more than one channel of DDR4 simultaneously?Mikael33 wrote:this topic doesn't seem very serious either
Oh, it's deadly serious assuming Lisa Su didn't flat-out lie at the end of AMD's webcast yesterday. Which, unlike the AMD fansquad around here, I actually watched live.
People tend to forget that I take technology, but not myself, seriously.
The story comments sections are littered with idiots who, quite curiously, tend to hold themselves in great esteem while still not being able to think through the ramifications of their object of worship.
Mr Bill wrote:On a slightly more serious note. Can't a particular core timeshare more than one channel of DDR4 simultaneously?
just brew it! wrote:My life in metaphore.Mr Bill wrote:On a slightly more serious note. Can't a particular core timeshare more than one channel of DDR4 simultaneously?
Not sure what you mean by this.
Mr Bill wrote:just brew it! wrote:Mr Bill wrote:On a slightly more serious note. Can't a particular core timeshare more than one channel of DDR4 simultaneously?
Not sure what you mean by this.
My life in metaphore.
I mean that if only one core was active, surely it could talk to more than one memory channel? If only two cores were active they could swap having those same channels. Slice the time enough and any one core can see those same memory channels... No? Or do I mean memory bank? I'm neither a hardware nor software engineer.
Mr Bill wrote:chuckula wrote:On a slightly more serious note. Can't a particular core timeshare more than one channel of DDR4 simultaneously?Mikael33 wrote:this topic doesn't seem very serious either
Oh, it's deadly serious assuming Lisa Su didn't flat-out lie at the end of AMD's webcast yesterday. Which, unlike the AMD fansquad around here, I actually watched live.
People tend to forget that I take technology, but not myself, seriously.
The story comments sections are littered with idiots who, quite curiously, tend to hold themselves in great esteem while still not being able to think through the ramifications of their object of worship.
Redocbew wrote:When there's an instruction that says "load this chunk of data" I don't believe the execution core of the CPU has any idea about memory channels, or even if the data is in main memory rather than being stored locally in a cache. My understanding is it's the memory controller(now usually also a part of the CPU) which would be responsible for the details on how requests get divided up into channels. I don't know the specifics about how that happens, but I'd be surprised to learn that it was a simple, static assignment of n cores across m channels. It's probably much more flexible than that.