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I'm sure everyone in the the enthusiast community knows about Intel's ham-fisted tech demo stunt. The real gist of the stunt is that Intel is going to be releasing customer-tier Skylake XCC SKUs in Q4 2018-Q1 2019.

This also means that Intel is going to be launching another HEDT chipset platform supporting LGA3647.

Here is what I suspect it will end-up being based what we already know about Purely platform.

Six-Channel DDR4 at 2400-2666Mhz supporting up to 192GiB of UDIMM (With the possibility of retaining ECC support due to HEDT competition from Threadripper)
44 PCIe 3.0 lanes
Same PCH as current X299 with a possible upgrade to 10Gb Ethernet.

The CPUs are going to be release under i9-8xxx family starting 18 cores scaling up by 2 cores increments until it reaches 28-cores. Their base clockspeeds are going to be ~2.6-2.8Ghz (to keep it manageable with air-cooling and energy-efficient when taxed) but their turbos speed are going to be ~4.5Ghz-4.8Ghz (5Ghz Turbo on the XE SKU) to ensure that they will beat Threadripper 2 at low-threaded workloads/content while contesting it at highly-threaded workloads/content. The real battle of these juggernauts is going to be energy efficiency front and I suspect they are going have their strong/weak points.

I'd be surprised if turbo clocks are north of 4.5 GHz.

Waco wrote:

I'd be surprised if turbo clocks are north of 4.5 GHz.

+1

I also cannot begin to imagine what they will price these things at!

Intel is really killing it with these anniversary editions! Right on the heels of the 8086k we now have the successor to the Gallatin Pentium 4 EE.

I'd be surprised if it boots successfully!

Krogoth said:

Here is what I suspect it will end-up being based what we already know about Purely platform.

While the demo system used was a Purley motherboard I wouldn't be surprised if the commercial product ends up on the LGA-2011 platform. The same chips running on LGA-2011 now also slot into LGA-3647, so it's not unprecedented.

chuckula wrote:

I'd be surprised if it boots successfully!

Krogoth said:

Here is what I suspect it will end-up being based what we already know about Purely platform.

While the demo system used was a Purley motherboard I wouldn't be surprised if the commercial product ends up on the LGA-2011 platform. The same chips running on LGA-2011 now also slot into LGA-3647, so it's not unprecedented.

Skylake-X XCC die is too large for Socket 2066 packaging which itself barely fits a Skylake-X HCC die. It has to be LGA 3647. You probably meant Socket 2066 since Socket 2011 is already phased out.

Krogoth wrote:

chuckula wrote:

I'd be surprised if it boots successfully!

Krogoth said:

Here is what I suspect it will end-up being based what we already know about Purely platform.

While the demo system used was a Purley motherboard I wouldn't be surprised if the commercial product ends up on the LGA-2011 platform. The same chips running on LGA-2011 now also slot into LGA-3647, so it's not unprecedented.

Skylake-X XCC die is too large for Socket 2066 packaging which itself barely fits a Skylake-X HCC die. It has to be LGA 3647. You probably meant Socket 2066 since Socket 2011 is already phased out.

The additional memory channels suggest a different socket as well, no? I also expect they'd want to spread the power delivery over more pins in order to improve thermal efficiency.

Incidentally, the newest unfounded speculation is that these parts will completely disable AVX-512 support.

As for the package, it's certainly possible for Intel to push LGA-3647 into the HEDT market, but I did an estimate and there's roughly 1400mm^2 of space under the heatspreader on an LGA-2066 (and LGA-2011, they are physically the same size) package (the entire PCB is over 2400 mm^2). Given that the XCC dies are estimated to be just under 700 mm^2, I don't see how it's impossible to fit one under the heatspreader. Don't let pictures of delidded HEDT chips fool you since there's another PCB in the package that can produce an optical illusion.

Isn't AVX-512 the new hotness? I mean, as a competitive advantage. Why would Intel disable it?

derFunkenstein wrote:

Isn't AVX-512 the new hotness? I mean, as a competitive advantage. Why would Intel disable it?

I'd be majorly disappointed if Intel turned off AVX-512 in HEDT parts.

But go take a look at TR's benchmark suite and see what (if any) benchmarks can even try to use AVX-512 whatsoever [even inefficiently since AVX-512 can hurt performance if you don't use right... kinda like DX12]. From what I can tell, the absolute newest versions of AIDA-64 have finally introduced some AVX-512 support. Incidentally these versions of AIDA-64 were released earlier this year and many months after TR last reviewed a Skylake X part.

So basically, we have a very powerful feature that Intel loves to sell for high-performance computing but that the consumer market doesn't seem to care about. Turning it off to bring Skylake X to "parity" with EpycRipper is one way that Intel might segment the chips.

While I don't want Intel to do it, it's almost worth it to hear the screams of indignation against Intel from the exact same people who have been calling AVX-512 idiotic and praising AMD for not even considering AVX-512 support since 2016. I'll add it to the completely disingenuous screams of outrage we heard when some Haswell parts didn't support TSX in 2013 (and Epyc doesn't support TSX in 2018 but suspiciously the same people didn't complain about it). Incidentally, TSX does have uses even for consumer programs.

well, for AVX-512 to get wide acceptance, a wide variety of tasks need to be able to use it on a wide variety of hardware. It's still pretty new, but I figure if it makes it into (for example) lots of video or audio production software and plugins, it'll be more important. Video transcoding would be another killer app if you can transcode very-high-quality video quickly. Apparently RPCS3 team is looking into incorporating it on supported platforms (the details are behind a Patreon paywall).

I highly doubt that Intel is going attempt to cram a Skylake-X XCC die in a Socket 2066 package. It is cheaper and easier for them to rebrand Xeon Platnium/Gold "rejects" and let motherboard vendors deal with hassle of making customer-tier LGA3647 boards.

It is essentially what AMD does with its Epyc "rejects". They keep the packaging but electrically axe half of the dice. It becomes a "Threadripper"

Krogoth wrote:

I highly doubt that Intel is going attempt to cram a Skylake-X XCC die in a Socket 2066 package. It is cheaper and easier for them to rebrand Xeon Platnium/Gold "rejects" and let motherboard vendors deal with hassle of making customer-tier LGA3647 boards.

It is essentially what AMD does with its Epyc "rejects". They keep the packaging but electrically axe half of the dice. It becomes a "Threadripper"

It's WCCftech so I wouldn't believe it 100%, but they claim that there is going to be both an LGA-2066 XCC chip (that only has 22 cores but is still Skylake XCC silicon) and the 28-core part on LGA-3647 that's going to be Cascade Lake instead of Skylake.

So if that happens Intel is pushing XCC silicon from different steppings into both LGA-2066 and a new HEDT LGA-3647 platform.

chuckula wrote:

But go take a look at TR's benchmark suite and see what (if any) benchmarks can even try to use AVX-512 whatsoever [even inefficiently since AVX-512 can hurt performance if you don't use right... kinda like DX12]. From what I can tell, the absolute newest versions of AIDA-64 have finally introduced some AVX-512 support. Incidentally these versions of AIDA-64 were released earlier this year and many months after TR last reviewed a Skylake X part.

So basically, we have a very powerful feature that Intel loves to sell for high-performance computing but that the consumer market doesn't seem to care about. Turning it off to bring Skylake X to "parity" with EpycRipper is one way that Intel might segment the chips.

While I don't want Intel to do it, it's almost worth it to hear the screams of indignation against Intel from the exact same people who have been calling AVX-512 idiotic and praising AMD for not even considering AVX-512 support since 2016. I'll add it to the completely disingenuous screams of outrage we heard when some Haswell parts didn't support TSX in 2013 (and Epyc doesn't support TSX in 2018 but suspiciously the same people didn't complain about it). Incidentally, TSX does have uses even for consumer programs.

Hey, those don't have to be internally inconsistent. I think Intel's push for wider SIMD in CPUs is misguided, but if we're going to have wide SIMD, support for the associated instructions could at least be a lot less messy. I'd much rather lean on thread-level parallelism than data-level parallelism both as a user and as a developer (yes, I'm weird), but I can't just ignore vectorization if I want to use the abilities of modern CPUs effectively. Whatever Intel decides, I'm stuck with. The real AMD fanboi move would be ignoring Intel's shenanigans entirely and doing whatever works best on AMD (where things are much more sane), but I am putting in the effort.

What I'd really like to see is even more decoupling of these instructions from the execution units backing them up. New vector instructions can be as wide as anyone cares to push them, but everything that can reasonably support them ought to support them. Meanwhile, there should be no pressure to make every implementation execute the widest instructions at 2 or even 1 per cycle. In fact, the widest instructions should usually be operating at half- or quarter-rate, so that when it is time to double up on hardware SIMD, the software to use it is already in place.

AMD is doing a great job at this, and has been for some time (Bulldozer etc is weird, but Bobcat and Jaguar are more clear examples of it). Intel is doing as nearly the exact opposite as they can, and we wonder why it's niche.

I'd say Intel is shooting themselves in the foot (with the biggest gun they can find) by making giant, power-hungry cores that depend on extra-wide vectorization to reach anything close to their full potential, and then not only failing to give software a push towards actually using those capabilities, but actively discouraging their use because the market segmentation guys apparently have priority over anyone with an actual clue.

As for the purely hardware side of things, it's great that there are cores out there individually capable of the kind of number-crunching SKL-X's are, but when Intel uses cores focused so heavily on that kind of performance across their whole lineup, they're just begging for someone with a more balanced design like Zen or Monsoon to show up and steal the average-workload efficiency crown (and the rest of the show along with it). I was hoping one of the ways Cannonlake and Cascade Lake would diverge would be Cannonlake keeping its feet on the ground with 256-bit FPUs, but that's looking unlikely.

At least the available designs have a bit of variety.

Waco wrote:

I'd be surprised if turbo clocks are north of 4.5 GHz.

For single and dual-threaded loads Skylake-X can easily handle 4.5Ghz+ and it will ensure that chips will beat Threadripper 2 at low-threaded applications. Ryzen+ has difficulty reaching 4.5Ghz without significant overvolting and I expect the same story for Threadripper 2. Obviously, the turbo-clocking will scale back the clockspeed as more cores are being harnessed.

Intel will achieve its marketing 5.0Ghz Q4 2018 goal set in E3 stunt demo by making it turbo speed on the XE SKU under single and dual-threaded loads.

Krogoth wrote:

Intel will achieve its marketing 5.0Ghz Q4 2018 goal set in E3 stunt demo by making it turbo speed on the XE SKU under single and dual-threaded loads.

I'm still gonna be surprised if it's that high. It takes a reasonably high amount of voltage to get those clocks stable in all workloads (and if I recall correctly it's above the "recommended max" that Intel specifies).

Waco wrote:

Krogoth wrote:

Intel will achieve its marketing 5.0Ghz Q4 2018 goal set in E3 stunt demo by making it turbo speed on the XE SKU under single and dual-threaded loads.

I'm still gonna be surprised if it's that high. It takes a reasonably high amount of voltage to get those clocks stable in all workloads (and if I recall correctly it's above the "recommended max" that Intel specifies).

If Intel is confident enough to release 8086K with a 5.0Ghz single-core turbo for ethusaist/epenis crowd. They'll certainly do it for XE version of Skylake-X XCC silicon. It'll give marketing types bragging rights "we have the fastest clockspeed* on a HEDT-tier CPU!"

Waco wrote:

Krogoth wrote:

Intel will achieve its marketing 5.0Ghz Q4 2018 goal set in E3 stunt demo by making it turbo speed on the XE SKU under single and dual-threaded loads.

I'm still gonna be surprised if it's that high. It takes a reasonably high amount of voltage to get those clocks stable in all workloads (and if I recall correctly it's above the "recommended max" that Intel specifies).

Add one more plus sign to however many they have now on 14nm and it should do it.
Anandtech's 8086k got up to 5GHz with just a smidge over 1.2V.

Krogoth wrote:

Waco wrote:

Krogoth wrote:

Intel will achieve its marketing 5.0Ghz Q4 2018 goal set in E3 stunt demo by making it turbo speed on the XE SKU under single and dual-threaded loads.

I'm still gonna be surprised if it's that high. It takes a reasonably high amount of voltage to get those clocks stable in all workloads (and if I recall correctly it's above the "recommended max" that Intel specifies).

If Intel is confident enough to release 8086K with a 5.0Ghz single-core turbo for ethusaist/epenis crowd. They'll certainly do it for XE version of Skylake-X XCC silicon. It'll give marketing types bragging rights "we have the fastest clockspeed* on a HEDT-tier CPU!"

The desktop 8086K is *very* different silicon from the Skylake X dies in the HEDT/Xeon platform.

They've got about the same voltage/frequency curves last I heard, though, and SKL-X has power delivery advantages, thermal advantages, and a lot more cores to spread the wear over.

Maybe I'm a bit out of date - I was under the impression the SK-X chips took significantly more voltage to get near 5 GHz even with a handful of cores over KL/CL.

Scanning the overclock.net thread on it, it looks like four-point-high at 1.3V or less is common enough. As I recall it, the real trouble is that 5 GHz is just too much heat, but as a one-core turbo that should be fine.

Skylake-X overclocks just as well as any of the mature 14nm silicon from Intel. The only difference is that Skylake-X has more cores to content with so you are more likely to get a core that doesn't want to dance. Obviously they scale up more quickly up the thermal and power consumption wall. That's why "5Ghz" is going to be limited to 1-2 threaded workloads and it scales back down when more cores are utillized. Ryzen+ and Threadrippers work the same way.