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Samsung's 5nm/2nm EUV tech, latest update

Fri Jul 12, 2019 12:06 am

https://www.nextbigfuture.com/2019/07/e ... eters.html

Compared to 7nm, Samsung’s 5nm FinFET process technology provides up to a 25 percent increase in logic area efficiency with 20 percent lower power consumption or 10 percent higher performance as a result of process improvement to enable us to have more innovative standard cell architecture


It was long considered a mature-to-the-point-of-diminishing-returns, the non-EUV processing that the whole chip industry was resigned to ‘deal with’ as the physics-bound end-point of sub-wavelength many-exposure nonlinear resist and advanced anisotropic molecular beam etching were able to achieve.


But the bottom line is that in silicon, the atom-to-atom crystal lattice spacing is something like 0.27 nanometers or so. Which is to say, that in a semiconductor gate which is only perhaps 5 nm in scale length, there are only 18 atoms of silicon in that scale.

Talk about “atomic foundry rules”! That’s pretty dense. At 2.0 nm, we’re only talking about 7 atoms of width. Gee! That’s mind-bogglingly impressive.


Interesting stuff, wonder when we'll start seeing this utilized for desktop processors.
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Re: Samsung's 5nm/2nm EUV tech, latest update

Fri Jul 12, 2019 9:59 am

I also wonder how durable these things will be. Smaller features means more susceptibility to electrical stresses that would not harm larger structures.
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