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JustAnEngineer
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AMD EPYC 7002 - Rome wasn't built at 14 nm

Wed Aug 07, 2019 7:25 pm

https://hothardware.com/reviews/amd-epy ... e-overview
Marco Chiappetta wrote:
EPYC 7002 series processors consist of 9 dies altogether (8 x CPU dies + 1 IO die) and max out with 64 physical cores per socket (128 threads). Rome maintains platform compatibility with existing first-gen EPYC parts, but significantly increases the platform’s capabilities in aggregate and per socket, and introduces a number of new features as well.
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Wed Aug 07, 2019 7:38 pm

JustAnEngineer wrote:
https://hothardware.com/reviews/amd-epyc-7002-series-architecture-overview
Marco Chiappetta wrote:
EPYC 7002 series processors consist of 9 dies altogether (8 x CPU dies + 1 IO die) and max out with 64 physical cores per socket (128 threads). Rome maintains platform compatibility with existing first-gen EPYC parts, but significantly increases the platform’s capabilities in aggregate and per socket, and introduces a number of new features as well.

So when is that 56 core cooper lake coming out? And what’s the TDP?

Also — how will AMD squander this seemingly huge advantage?
 
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Wed Aug 07, 2019 7:58 pm

Another review:

https://www.servethehome.com/amd-epyc-7 ... -knockout/
From Page 7
The AMD EPYC 7402P with 24 cores is priced as an Intel Xeon Gold 5218 competitor. With more cores, it is able to push ahead being over twice as fast. That is a big deal. The Intel Xeon Gold 6209U is a $1350 version of the Intel Xeon Gold 6230 CPU that is single socket only. Here, the AMD EPYC 7402P is about two thirds faster yet 10% less expensive.
 
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Wed Aug 07, 2019 8:03 pm

https://hothardware.com/reviews/amd-epy ... e-overview
https://hothardware.com/news/amd-launch ... ell-lenovo
Marco Chiappetta wrote:
Rome 7nm EPYC 7002 series processors maintain platform compatibility with existing first-gen EPYC parts.
EPYC 7742 has 64 cores / 128 threads at 2.25GHz to 3.4GHz, 256 MB L3 cache, 225W to 240W configurable TDP.

blastdoor wrote:
So when is that 56 core cooper lake coming out? And what’s the TDP?

https://hothardware.com/news/intel-56-c ... iving-2020
Paul Lilly wrote:
Intel's new Cooper Lake family will stretch its 14+++++ nm technology for another round of Xeon processors. Intel's Cooper Lake Xeon Platinum 9200 series will introduce a new socket. Intel is planning to roll out its Cooper Lake lineup sometime in the first half of 2020.
Xeon Platinum 9282 will have 56 cores / 112 threads at 2.6GHz to 3.8GHz, 77MB L3 cache, 400W TDP.
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Thu Aug 08, 2019 6:07 am

I also read the Phoronix review.

Man, this thing is a beast. In everything but the most heavily optimized AVX-512 tests, the new Epyc absolutely crushes Xeon by every available metric.

From my Apple-user perspective, it looks like Apple made a big mistake going with Intel in the new Mac Pro. The Mac Pro isn't even out yet and it would now appear to be utterly destroyed from both a raw performance and price/performance perspective. I've been using a headless Linux threadripper system for the past year, remoting in from my iMac. I had hoped that Apple's new Mac Pro efforts would entice me back to a pure Mac setup, but I just can't see that happening. If Apple insists on sticking with Intel (and apparently they do), then 10nm Sunny Cove Xeons are desperately needed.
 
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Thu Aug 08, 2019 9:04 am

It is the K8 Operton all over again. AMD has very compelling options in 1P/2P market if your organization is scheduled for an upgrade/overhaul. Intel doesn't have a viable competitor at current price/performance ranges and will likely not have one until 2021-2022. The only way for Intel to fight it off in the near-future is through an unenviable(for shareholders) price war.
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Thu Aug 08, 2019 9:52 am

Krogoth wrote:
It is the K8 Operton all over again. AMD has very compelling options in 1P/2P market if your organization is scheduled for an upgrade/overhaul. Intel doesn't have a viable competitor at current price/performance ranges and will likely not have one until 2021-2022. The only way for Intel to fight it off in the near-future is through an unenviable(for shareholders) price war.


I sure hope this ends better for AMD than the Opteron experience.

This time around, AMD has two big advantages that they previously lacked:

1. they are no longer constrained to use their own (or GloFo's) fabs, and the investments that TSMC and Samsung have made (fueled by profits from smartphones), means Intel is no longer leading in fab tech (and probably never will again, or at least not by the margin they once led -- it looks like it will likely be neck and neck from here out)

2. their CEO appears to have *much* better judgement about how to make strategic investments than Ruiz did. If Rome is profitable, hopefully they will invest those profits wisely, rather than blowing them on some overpriced acquisition.

One other thought -- if Zen 3 ends up being competitive with Sunny Cove, then stick a fork in Intel's 60% margins -- they'll be gone forever. I'm not saying Intel is dying, I'm just saying their days of sucking up all the profit in PCs/servers will be over.
 
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Thu Aug 08, 2019 9:58 am

You guys have no idea how excited I am for these for storage / IO servers. :)
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Thu Aug 08, 2019 10:19 am

Waco wrote:
You guys have no idea how excited I am for these for storage / IO servers. :)


128 PCIe 3.0/4.0 lanes per chip = I/O bandwidth, I/O bandwidth everywhere....... :D
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Thu Aug 08, 2019 11:15 am

Along with plenty of CPU grunt, enough memory channels, and ridiculously good pricing.
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Fri Aug 09, 2019 11:52 am

https://www.servethehome.com/amd-epyc-7 ... ockout/10/

"If AMD EPYC 7002, with a massive core count, memory bandwidth, PCIe generation and lane count, power consumption, and pricing advantage cannot take significant share, we are basically done. If AMD does not gain enormous share with this much of a lead, and easy compatibility, Intel officially has a monopoly on the market and companies like Ampere and Marvell should shut down their Arm projects. If AMD does not gain significant share, there is no merit to having a wholistically better product than Intel."

Holy ****, I don't think I've ever heard such an endorsement for a product!
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Fri Aug 09, 2019 8:51 pm

This is an unequivocal home run for AMD in the server. Only unknown keeping it from a grand slam is supply which I foresee them being able to see every chip that they can make for the next year.

Of course my ego can think of a few things more that I wish AMD did:
  • Quad socket support
  • On package option for Vega 20 accelerator option - 32 GB of HBM backed by up to 4 TB of DDR4 on a 512 bit wide bus is an interesting proposal.
  • Single chiplet, high clock/high power model (think Ryzen 3000 clocks)

Milan is the next server product which the bar has been set incredibly high for. If AMD though they would be up against Ice Lake SP vs. Rome (and two years ago, I would have thought the same), I wonder what they though Milan would be up against. It had to have entered development when Tiger Lake for server rumors first started to float around (this has since become Sapphire Rapids). I simply see AMD enhancing the chiplets next go around and re-use the current IO die for the next generation. No pressing need to update the IO die until DDR5 and PCIe 5.0 are ready. The current topology from what I understand is that on-die CCX traffic has to hit the IO chip which would imply two links with the IO die handling traffic. My Milan prediction is that they increase the size of the CCX to incorporate all eight core and unify the L3 cache on each chiplet. The effect is an efficiency gain. Beyond that I would expect AMD to adopt AVX-512 but continue to leverage their existing 256 bit wide SIMD units. Peak performance won't move with AVX-512 support but there is some efficiency gains to be had from using the mask registers and new instructions.
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Tue Sep 24, 2019 11:50 am

The next AMD server architecture is rumored to support four-socket systems four threads per core.
https://www.techpowerup.com/259505/amd- ... ur-way-smt
Last edited by JustAnEngineer on Tue Sep 24, 2019 2:37 pm, edited 1 time in total.
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Tue Sep 24, 2019 1:09 pm

JustAnEngineer wrote:
The next AMD server architecture is rumored to support four-socket systems.
https://www.techpowerup.com/259505/amd- ... ur-way-smt

That article mentions 4 threads per core, not 4 sockets per system. Did I miss something?
 
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Tue Sep 24, 2019 1:19 pm

Usacomp2k3 wrote:
JustAnEngineer wrote:
The next AMD server architecture is rumored to support four-socket systems.
https://www.techpowerup.com/259505/amd- ... ur-way-smt

That article mentions 4 threads per core, not 4 sockets per system. Did I miss something?

Sure looks like it is talking about 4 threads per core to me too.

And my knee-jerk reaction to that was: "Oh great, because optimal thread scheduling isn't hard enough already with 2-way SMT and individual cores that top out at different boost clocks".
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Tue Sep 24, 2019 2:22 pm

just brew it! wrote:
And my knee-jerk reaction to that was: "Oh great, because optimal thread scheduling isn't hard enough already with 2-way SMT and individual cores that top out at different boost clocks".


With all these threads and Infinity Fabrics maybe they should have called it Weaver.
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Tue Sep 24, 2019 2:38 pm

Usacomp2k3 wrote:
That article mentions 4 threads per core, not 4 sockets per system. Did I miss something?
Doh! :oops:
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Tue Sep 24, 2019 3:10 pm

I'm not ready to process next gen information. I'm still trying to process my simultaneous disappointment and relief that I never saw any Epyc "THIC" jokes in regards to the 7H12.
 
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Tue Sep 24, 2019 4:08 pm

4 threads per core would be interesting. It's yet another way to get the most throughput out of the CCXs that can clock the highest (assuming your workload isn't super resource intensive).
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Tue Sep 24, 2019 4:33 pm

Waco wrote:
4 threads per core would be interesting. It's yet another way to get the most throughput out of the CCXs that can clock the highest (assuming your workload isn't super resource intensive).

I believe SMT helps with memory latency, too, which makes sense with all them cores.
 
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Tue Sep 24, 2019 4:38 pm

blastdoor wrote:
Waco wrote:
4 threads per core would be interesting. It's yet another way to get the most throughput out of the CCXs that can clock the highest (assuming your workload isn't super resource intensive).

I believe SMT helps with memory latency, too, which makes sense with all them cores.

It helps mask memory latency by potentially giving execution units which would otherwise sit idle something else to do while they wait on the DRAM. IOW it can help improve net IPC in multi-threaded workloads. But it isn't making memory latency any better in an absolute sense, nor improving single-threaded performance.
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Tue Sep 24, 2019 5:33 pm

http://yosefk.com/blog/amdahls-law-in-reverse-the-wimpy-core-advantage.html

Being able to wait on more things at once without (in theory) sacrificing anything on the Amdahl's law side is great, though I'm not convinced 2019's scheduling is good enough for 4-way SMT on the desktop.
 
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Wed Sep 25, 2019 1:50 am

just brew it! wrote:
blastdoor wrote:
Waco wrote:
4 threads per core would be interesting. It's yet another way to get the most throughput out of the CCXs that can clock the highest (assuming your workload isn't super resource intensive).

I believe SMT helps with memory latency, too, which makes sense with all them cores.

It helps mask memory latency by potentially giving execution units which would otherwise sit idle something else to do while they wait on the DRAM. IOW it can help improve net IPC in multi-threaded workloads. But it isn't making memory latency any better in an absolute sense, nor improving single-threaded performance.

Yup — that’s what I meant :-)
 
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Thu Sep 26, 2019 8:18 pm

https://hothardware.com/news/amd-epyc-s ... 10-percent
A new report coming out of Taiwan is suggesting that orders for EPYC 7002 processor have been so strong thus far that AMD could see a dramatic upswing in market share during 2020 as more vendors adopt the processors. If market analysts are correct, AMD could be looking at a 10 percent share of the server market by the end of 2020.
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Mon Oct 07, 2019 5:55 am

Info on Zen3 has leaked from an AMD presentation. Each generation of AMD server CPUs shows 5½ quarters from tapeout to release, making Zen3 based Milan processors available in the second half of 2020.
https://www.techpowerup.com/259869/amd- ... pdated-smt
https://hothardware.com/news/amd-epyc-z ... ocket-ddr5
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Wed Oct 30, 2019 6:33 pm

Waco wrote:
You guys have no idea how excited I am for these for storage / IO servers. :)
Cray is apparently excited that you're excited...
https://www.anandtech.com/show/15048/cr ... s-per-rack
Cray’s entry-level ClusterStor E1000 will offer about 60 TB of usable capacity while providing around 30 GB/s throughput. When scaled to its highest performance levels, the ClusterStor E1000 will deliver up to 1.6 TB/s sequential read/write speed and up to 50,000 IOPS per rack. Clients with more than one rack will naturally get higher performance.

Specially configured ClusterStor E1000 external storage systems will be used by Cray’s upcoming Aurora, Frontier, and El Capitan exascale supercomputers, which will feature over 1.3 ExaBytes of total storage space. Furthermore, the National Energy Research Scientific Computing Center (NERSC) will use a 30 PB all-flash ClusterStor E1000.
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Wed Oct 30, 2019 6:43 pm

Yep. I work with the ClusterStor design team pretty closely on occasion. Smart bunch!
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Wed Oct 30, 2019 6:55 pm

the wrote:
This is an unequivocal home run for AMD in the server. Only unknown keeping it from a grand slam is supply which I foresee them being able to sell every chip that they can make for the next year.

Milan is the next server product which the bar has been set incredibly high for. If AMD thought they would be up against Ice Lake-SP vs. Rome (and two years ago, I would have thought the same), I wonder what they thought Milan would be up against.


It looks like Ice Lake-SP will arrive around the same time as Milan.
https://hothardware.com/news/intel-10nm ... 76-threads
Intel is planning to make Ice Lake-SP available in up to 38-core/76-thread configurations (per socket) with a TDP (Thermal Design Power) of 270 watts. Other features include support for 64 PCIe 4.0 lanes, 8-channel DDR4-3200 memory (16 DIMMs per socket) and Intel's second-gen Optane DC Persistent Memory. Intel is targeting a Q3 2020 launch for Ice Lake-SP.


https://www.wepc.com/news/amd-inadverte ... rver-cpus/
AMD’s Zen 3-based Epyc Milan chips use 7nm+ node tech to bring about a boost to performance per watt that surpasses that of Intel’s 10nm Ice Lake-SP Xeon CPUs. Epyc Milan features 64 cores and 128 threads, SP3 socket compatibility (meaning backward compatibility with existing platforms), a TDP ranging from 120 W to 225 W depending on the SKU, PCIe 4.0 interface, and DDR4 memory support. Epyc Milan is touted for release in 2020.
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Tue Nov 12, 2019 1:06 pm

EPYC 7H12 looks strong in geekbench.
https://hothardware.com/news/amd-64-cor ... ercomputer
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Wed Nov 13, 2019 4:01 am

JustAnEngineer wrote:
EPYC 7H12 looks strong in geekbench.
https://hothardware.com/news/amd-64-cor ... ercomputer


Looks like that's Geekbench 4 rather than 5.

I have the impression that Geekbench 4 scales linearly with CPU cores whereas 5 doesn't. I guess which is more appropriate... "depends on the workload".

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