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JustAnEngineer
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Tue Apr 14, 2020 6:11 pm

https://www.techpowerup.com/265761/new- ... -workloads
The three new processors, the AMD EPYC 7F32 (8 cores), EPYC 7F52 (16 cores) and EPYC 7F72 (24 cores), expand 2nd Gen AMD EPYC performance leadership into workloads that can leverage up to 500 MHz of additional base frequency, and large amounts of cache, making AMD EPYC the world's highest per core performance x86 server CPU.
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Tue Apr 14, 2020 8:59 pm

JustAnEngineer wrote:
https://www.techpowerup.com/265761/new-2nd-gen-amd-epyc-processors-redefine-performance-for-database-commercial-hpc-and-hyperconverged-workloads
The three new processors, the AMD EPYC 7F32 (8 cores), EPYC 7F52 (16 cores) and EPYC 7F72 (24 cores), expand 2nd Gen AMD EPYC performance leadership into workloads that can leverage up to 500 MHz of additional base frequency, and large amounts of cache, making AMD EPYC the world's highest per core performance x86 server CPU.


So, I don't know much about this stuff, but I've heard that there's a tradeoff between power, performance, and area.

This leads me to wonder -- if AMD (or anybody else) really wanted to focus on single thread performance, what if they held area constant at, say, Sandybridge density and then put the pedal to the metal in terms of power and performance. What frequency could be achieved?

furthermore... suppose one were to design a heterogenous CPU with one or two cores running hot, fast, and low-density with another 16 or so cores running slow, cool, and high density? Is there a reason nobody is trying that?
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JustAnEngineer
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Tue Apr 14, 2020 9:42 pm

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JustAnEngineer
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Tue Apr 14, 2020 10:15 pm

https://www.anandtech.com/show/15715/am ... -frequency
 AMD EPYC 7002 'Rome' Processors (2P)
             Core/Thread  Min(GHz)Max     L3       TDP      Price
EPYC 7742     64 /128    2.25    3.40    256 MB    225 W    $6950
EPYC 7702     64 /128    2.00    3.35    256 MB    200 W    $6450
EPYC 7642     48 / 96    2.30    3.20    256 MB    225 W    $4775
EPYC 7552     48 / 96    2.20    3.30    192 MB    200 W    $4025
EPYC 7542     32 / 64    2.90    3.40    128 MB    225 W    $3400
EPYC 7502     32 / 64    2.50    3.35    128 MB    200 W    $2600
EPYC 7452     32 / 64    2.35    3.35    128 MB    155 W    $2025
EPYC 7402     24 / 48    2.80    3.35    128 MB    155 W    $1783
EPYC 7352     24 / 48    2.30    3.20    128 MB    180 W    $1350
EPYC 7302     16 / 32    3.00    3.30    128 MB    155 W    $ 978
EPYC 7282     16 / 32    2.80    3.20     64 MB    120 W    $ 650
EPYC 7272     12 / 24    2.90    3.20     64 MB    155 W    $ 625
EPYC 7262      8 / 16    3.20    3.40    128 MB    120 W    $ 575
EPYC 7252      8 / 16    3.10    3.20     64 MB    120 W    $ 475
AMD EPYC 7002 Rome Processors (1P)
EPYC 7702P    64 /128    2.00    3.35    256 MB    200 W    $4425
EPYC 7502P    32 / 64    2.50    3.35    128 MB    200 W    $2300
EPYC 7402P    24 / 48    2.80    3.35    128 MB    200 W    $1250
EPYC 7302P    16 / 32    3.00    3.30    128 MB    155 W*    $825
EPYC 7232P     8 / 16    3.10    3.20     32 MB    120 W     $450           
AMD EPYC 7H Rome Processors (1P)
EPYC 7H12     64 /128    2.60    3.30    256 MB    280 W    $?
AMD EPYC 7F Rome Processors (1P)
EPYC 7F72     24 / 48    3.20    3.70    192 MB    240 W    $2450
EPYC 7F52     16 / 32    3.50    3.90    256 MB    240 W    $3100
EPYC 7F32      8 / 16    3.70    3.90    128 MB    180 W    $2100 
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Wed Apr 15, 2020 10:00 am

JustAnEngineer wrote:


That's not quite what I had in mind.

I was thinking of a CPU that looks more like this:

1. two Zen2 class cores, on a TSMC 7nm process, BUT with transistor density more like what we saw with Sandybridge cores on Intel 32nm. So, for these two cores, put all the benefits of process improvements into higher clock speeds. What would that get us in terms of clock speed? 6 GHz? more?

2. 8 to 16 Zen2 class cores, TSMC 7nm process, BUT with transistor density more like an iPhone SOC and much lower clock speeds (say, 2 GHz).

This would be different from Alder Lake, because the cores are all the same architecture -- they're just varying in transistor density and clock speed.

Is this a stupid idea?
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Wed Apr 15, 2020 12:31 pm

Take a look at the differences between zen and zen +.

Some of that is what they did going from a 14nm process to a 12nm process.

The chip layout was almost the same using smaller lithography and this allowed them to do a quick respin, grab some low hanging fruit, and really ramp up the frequency.

I beleive this is also the same thing they did with the 1600AF
old design on a newer process for a awesome cheap chip tat clocks well.
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Wed Apr 15, 2020 3:36 pm

blastdoor wrote:
JustAnEngineer wrote:


That's not quite what I had in mind.

I was thinking of a CPU that looks more like this:

1. two Zen2 class cores, on a TSMC 7nm process, BUT with transistor density more like what we saw with Sandybridge cores on Intel 32nm. So, for these two cores, put all the benefits of process improvements into higher clock speeds. What would that get us in terms of clock speed? 6 GHz? more?

2. 8 to 16 Zen2 class cores, TSMC 7nm process, BUT with transistor density more like an iPhone SOC and much lower clock speeds (say, 2 GHz).

This would be different from Alder Lake, because the cores are all the same architecture -- they're just varying in transistor density and clock speed.

Is this a stupid idea?


Cores, caches, I/O and other parts of a CPU can't be stretched out in a quick and dirty way. Making everything bigger would add tens of picoseconds to signal propagation times, and this matters a lot when clock cycle is 200 ps or less. The design would have to be re-simulated, re-tuned, re-tested and more - take a look at this to get a taste of how complex this topic can get:
https://web.stanford.edu/class/archive/ee/ee371/ee371.1066/lectures/lect_11_2up.pdf

Apart from this, my uninformed guess is that this kind of on-chip heterogenity has no use in servers. Even if some use cases did (or do) require both slower, efficient cores and faster, less efficient ones, server operators would buy whole racks of each kind, and optimize each for its purpose.
 
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Wed Apr 15, 2020 6:20 pm

Wirko wrote:
blastdoor wrote:
JustAnEngineer wrote:


That's not quite what I had in mind.

I was thinking of a CPU that looks more like this:

1. two Zen2 class cores, on a TSMC 7nm process, BUT with transistor density more like what we saw with Sandybridge cores on Intel 32nm. So, for these two cores, put all the benefits of process improvements into higher clock speeds. What would that get us in terms of clock speed? 6 GHz? more?

2. 8 to 16 Zen2 class cores, TSMC 7nm process, BUT with transistor density more like an iPhone SOC and much lower clock speeds (say, 2 GHz).

This would be different from Alder Lake, because the cores are all the same architecture -- they're just varying in transistor density and clock speed.

Is this a stupid idea?


Cores, caches, I/O and other parts of a CPU can't be stretched out in a quick and dirty way. Making everything bigger would add tens of picoseconds to signal propagation times, and this matters a lot when clock cycle is 200 ps or less. The design would have to be re-simulated, re-tuned, re-tested and more - take a look at this to get a taste of how complex this topic can get:
https://web.stanford.edu/class/archive/ee/ee371/ee371.1066/lectures/lect_11_2up.pdf

Apart from this, my uninformed guess is that this kind of on-chip heterogenity has no use in servers. Even if some use cases did (or do) require both slower, efficient cores and faster, less efficient ones, server operators would buy whole racks of each kind, and optimize each for its purpose.


Good point regarding servers... I guess it would end up being a pretty niche market for this approach, which is maybe why it hasn't been done.
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Wed Apr 15, 2020 8:05 pm

In a few years I'll have an interesting tale to tell about this...but I would guess this forum will be long-gone by then. :cry:
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JustAnEngineer
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Re: AMD EPYC 7002 - Rome wasn't built at 14 nm

Wed Apr 29, 2020 7:01 pm

https://www.techpowerup.com/266424/amd- ... 3-platform
"Powered by the AMD EPYC 7742 processor, the Oracle Cloud E3 Platform enables customers to run high performance computing (HPC) workloads such as risk simulations, molecular modeling, and contextual search."
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