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Wirko
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Re: 5 nm chips in 2020

Tue Dec 10, 2019 11:03 am

Igor_Kavinski wrote:
https://www.techspot.com/news/83078-haswell-back-intel-reverses-decision-discontinue-22nm-pentium.html

Haswell, welcome back from the dead :lol:

https://wccftech.com/intel-ceo-beyond-cpu-7nm-more/


Funny things happen if you apply the ++ operator on the constant 14 enough times.
 
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Re: 5 nm chips in 2020

Tue Dec 10, 2019 11:10 am

just brew it! wrote:
Aranarth wrote:
just brew it! wrote:
I believe TSMC's 7nm process is already on EUV.

it is not.
7+ from tsmc will be EUV when it arrives.

Ahh, guess I got 7 confused with 7+!


Don't worry!

I'm sure there will be a 7+++++++++ process eventually because everyone wants to emulate intel. :D
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Re: 5 nm chips in 2020

Tue Dec 10, 2019 11:31 am

Wirko wrote:
Funny things happen if you apply the ++ operator on the constant 14 enough times.

Indeed. Especially given that applying an operator that expects an lvalue to a constant isn't going to end well. :wink:

Geek trivia tangent:

Back in the early days (no idea if any modern compilers still have this issue), some Fortran compilers did not strictly guard against this sort of thing in all situations. Arguments to functions were passed by reference, and to conserve scarce memory, all references to the same constant resolved to the same shared copy of that constant. So if you passed a constant as a function argument, and the function subsequently tried to assign something to the argument, you could arbitrarily change the value of a constant (with the new value subsequently being used everywhere in the program until the program was restarted).

The running joke was something to the effect of "Have you ever accidentally (or intentionally) changed the value of 1?" Talk about bizarre, difficult-to-diagnose bugs...
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Re: 5 nm chips in 2020

Tue Dec 10, 2019 12:02 pm

just brew it! wrote:
...some Fortran compilers did not strictly guard against this sort of thing in all situations...


I wonder how many scientists went bald trying to debug their programs using such compilers :lol:
 
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Re: 5 nm chips in 2020

Tue Dec 10, 2019 12:07 pm

Igor_Kavinski wrote:
just brew it! wrote:
...some Fortran compilers did not strictly guard against this sort of thing in all situations...

I wonder how many scientists went bald trying to debug their programs using such compilers :lol:

They were probably still thankful they had something higher-level than assembly language to program in.
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Wirko
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Re: 5 nm chips in 2020

Tue Dec 10, 2019 6:04 pm

just brew it! wrote:
Back in the early days (no idea if any modern compilers still have this issue), some Fortran compilers did not strictly guard against this sort of thing in all situations. Arguments to functions were passed by reference, and to conserve scarce memory, all references to the same constant resolved to the same shared copy of that constant. So if you passed a constant as a function argument, and the function subsequently tried to assign something to the argument, you could arbitrarily change the value of a constant (with the new value subsequently being used everywhere in the program until the program was restarted).

If each reference takes up, say, 16 bits, and an integer constant takes up 16 bits too, how much of that scarce memory do you save?
 
JustAnEngineer
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Re: 5 nm chips in 2020

Tue Dec 10, 2019 6:07 pm

Having used BASIC for seven years made FORTRAN seem easy to me when I got into college. What blew my mind was how C would very easily allow you to do things like index beyond the end of an array, usually with catastrophic results.
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Re: 5 nm chips in 2020

Tue Dec 10, 2019 7:37 pm

Wirko wrote:
just brew it! wrote:
Back in the early days (no idea if any modern compilers still have this issue), some Fortran compilers did not strictly guard against this sort of thing in all situations. Arguments to functions were passed by reference, and to conserve scarce memory, all references to the same constant resolved to the same shared copy of that constant. So if you passed a constant as a function argument, and the function subsequently tried to assign something to the argument, you could arbitrarily change the value of a constant (with the new value subsequently being used everywhere in the program until the program was restarted).

If each reference takes up, say, 16 bits, and an integer constant takes up 16 bits too, how much of that scarce memory do you save?

Single-precision floats are 32 bits, and double-precision are 64 bits. And since it's a pass-by-reference language you'll need the reference anyway. So you potentially save 32 or 64 bits each time.
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Re: 5 nm chips in 2020

Wed Dec 11, 2019 12:53 am

just brew it! wrote:
Wirko wrote:
Funny things happen if you apply the ++ operator on the constant 14 enough times.

Indeed. Especially given that applying an operator that expects an lvalue to a constant isn't going to end well. :wink:

Geek trivia tangent:

Back in the early days (no idea if any modern compilers still have this issue), some Fortran compilers did not strictly guard against this sort of thing in all situations. Arguments to functions were passed by reference, and to conserve scarce memory, all references to the same constant resolved to the same shared copy of that constant. So if you passed a constant as a function argument, and the function subsequently tried to assign something to the argument, you could arbitrarily change the value of a constant (with the new value subsequently being used everywhere in the program until the program was restarted).

The running joke was something to the effect of "Have you ever accidentally (or intentionally) changed the value of 1?" Talk about bizarre, difficult-to-diagnose bugs...


Don't worry, Java continues the tradition.

https://stackoverflow.com/questions/150 ... 128-number

https://stackoverflow.com/questions/170 ... pers-in-ja

Some dumbass who decided that "Integer" should be an object, and that there should be an "Integer" cache of int values to accelerate some Integer operations. As such, Integer(100) will be cached, but Integer(128) will not be. You need to call the object .equals() operator instead of == (which is a plain-old reference compare).

And people say that Java simplified things by removing pointers...
 
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Re: 5 nm chips in 2020

Wed Dec 11, 2019 7:14 am

Never under-estimate the ingenuity of a well-meaning but inexperienced (and inadequately supervised) developer on a mission. The code I maintain at my day job drives that point home on a daily basis. (Original dev spent a couple of years creating a massive dumpster fire, then rage-quit.)

The fact that Python is easy to learn and makes it easy to quickly prototype things is a double-edged sword. Unless you've got suitable controls in place, a lot of half-baked stuff can make it into production code...
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Re: 5 nm chips in 2020

Wed Dec 11, 2019 8:15 am

https://www.anandtech.com/show/15217/in ... 19-to-2029

This is the first mention on 1.4nm in the context of Intel on any Intel-related slide. For context, if that 1.4nm is indicative of any actual feature, would be the equivalent of 12 silicon atoms across.


https://www.inverse.com/article/61384-m ... re-compute

Jim Keller, Senior Vice President of Intel’s Silicon Engineering Group said Tuesday at MIT Technology Review’s Future Compute conference that Moore’s Law — a refresher definition is below — won’t be dead for at least another 30 years or so.


WTH????!
 
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Re: 5 nm chips in 2020

Wed Dec 11, 2019 9:55 am

Igor_Kavinski wrote:
Jim Keller, Senior Vice President of Intel’s Silicon Engineering Group said Tuesday at MIT Technology Review’s Future Compute conference that Moore’s Law — a refresher definition is below — won’t be dead for at least another 30 years or so.

WTH????!

I suspect that in the context of traditional silicon chips, it will be. You can't really argue with the laws of physics, and as pointed out above traditional silicon chip features are approaching atomic scale. But innovative new materials and/or techniques will eventually be developed. So I expect Moore's Law will continue to slow down (or possibly even go on hiatus) for a few years as the industry sorts that out. But it'll eventually pick up again.
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Re: 5 nm chips in 2020

Wed Dec 11, 2019 5:57 pm

Igor_Kavinski wrote:
https://www.anandtech.com/show/15217/intels-manufacturing-roadmap-from-2019-to-2029

This is the first mention on 1.4nm in the context of Intel on any Intel-related slide. For context, if that 1.4nm is indicative of any actual feature, would be the equivalent of 12 silicon atoms across.


https://www.inverse.com/article/61384-m ... re-compute

Jim Keller, Senior Vice President of Intel’s Silicon Engineering Group said Tuesday at MIT Technology Review’s Future Compute conference that Moore’s Law — a refresher definition is below — won’t be dead for at least another 30 years or so.


WTH????!


30 years? Is he trying to make 3d stacking count as a way to keep Moore's Law alive? If so, that's not exactly a cheat but it's not not a cheat either.

In any event, the binding constraint on Moore's Law is likely to be economics, not physics/engineering. And that constraint might bind Intel before it binds TSMC. So yeah... if you stretch the interpretation of Moore's Law AND spend gazillions of dollars on R&D and capex, maybe 30 more years is possible.

But will x86 provide the sales volume for Intel to justify the gazillions on R&D and capex, given that x86 is effectively shut out of mobile and wearables? And what if Intel starts to lose share in PCs/servers? Then where is the volume coming from? 5g phone modems? oops, guess snot. But ok, 5g for non-phones? How big is that market? And what are Intel's margins there as they compete with Qualcomm and the Chinese?

I can believe that maybe Moore's Law continues for TSMC, but Intel? I doubt it, unless Intel management has a major come-to-Jesus moment, and quick.
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Re: 5 nm chips in 2020

Thu Dec 12, 2019 3:58 am

blastdoor wrote:
that's not exactly a cheat but it's not not a cheat either.


D'oh. So it's a quantum cheat.

What about 2D integration, for example wafer scale integration? Is that cheating or not or not not? Moore's law is just "the observation that the number of transistors in a dense integrated circuit doubles about every two years" (Wikipedia) and you can't say today's ICs aren't dense.
 
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Re: 5 nm chips in 2020

Thu Dec 12, 2019 6:25 am

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Re: 5 nm chips in 2020

Thu Dec 12, 2019 8:34 am

Wirko wrote:
blastdoor wrote:
that's not exactly a cheat but it's not not a cheat either.


D'oh. So it's a quantum cheat.

What about 2D integration, for example wafer scale integration? Is that cheating or not or not not? Moore's law is just "the observation that the number of transistors in a dense integrated circuit doubles about every two years" (Wikipedia) and you can't say today's ICs aren't dense.


Seems like 2d integration is kind of a one-off that isn't going to double density every 24 months for the next 30 years, or am I misunderstanding what you mean?

The reason I say 3d stacking both is and is not a cheat is that Moore's Law is silent regarding the 3rd dimension. It only talks about transistor density within a 2d area. Counting transistors stacked above as an increase in 2d density isn't specifically ruled out in the Law, and so it's not exactly a cheat. But it sure does seem to violate the spirit of the Law as commonly understood, so it's not not a cheat either.

A 3d Moore's Law would probably focus on density of transistors within a volume, rather than an area, and so 3d stacking would not represent an improvement.
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Re: 5 nm chips in 2020

Thu Dec 12, 2019 10:20 am

Wirko wrote:
What about 2D integration, for example wafer scale integration? Is that cheating or not or not not? Moore's law is just "the observation that the number of transistors in a dense integrated circuit doubles about every two years" (Wikipedia) and you can't say today's ICs aren't dense.

Wafer-scale integration does not increase density, you're just making bigger chips. Which is bad for yield.

Current trends are actually in the opposite direction, with MCMs like the current AMD generation becoming more common. Lets you keep yields up while still increasing the number of transistors in a single package.
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Re: 5 nm chips in 2020

Thu Dec 12, 2019 5:10 pm

just brew it! wrote:
Wafer-scale integration does not increase density, you're just making bigger chips. Which is bad for yield.


The only current attempt that I know of is Cerebras, and they say they can work around the defective "cells" somehow. Sure they can, and they absolutely have to in order to make a working chip, but some additional logic and interconnects are necessary to do that, plus spare cells.
 
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Re: 5 nm chips in 2020

Thu Dec 12, 2019 5:31 pm

Wirko wrote:
just brew it! wrote:
Wafer-scale integration does not increase density, you're just making bigger chips. Which is bad for yield.

The only current attempt that I know of is Cerebras, and they say they can work around the defective "cells" somehow. Sure they can, and they absolutely have to in order to make a working chip, but some additional logic and interconnects are necessary to do that, plus spare cells.

Yup. And I'm not convinced this will end up being more economical (or more performant) than using some sort of large/dense MCM.
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Re: 5 nm chips in 2020

Thu Dec 12, 2019 6:13 pm

blastdoor wrote:
Seems like 2d integration is kind of a one-off that isn't going to double density every 24 months for the next 30 years, or am I misunderstanding what you mean?

The reason I say 3d stacking both is and is not a cheat is that Moore's Law is silent regarding the 3rd dimension. It only talks about transistor density within a 2d area. Counting transistors stacked above as an increase in 2d density isn't specifically ruled out in the Law, and so it's not exactly a cheat. But it sure does seem to violate the spirit of the Law as commonly understood, so it's not not a cheat either.

A 3d Moore's Law would probably focus on density of transistors within a volume, rather than an area, and so 3d stacking would not represent an improvement.


Yes, 2D integration is a one-off since we can't extend it indefinitely. 3D stacking is a one-off too. Barely legal according to the Law.

But then there's lithographic layering. I'm not sure if that's the proper term; that's how Toshiba, Samsung and others stack about 128 NAND storage cells on top of each other, all on a single die. They're planning to make much higher stacks going forward (https://semiengineering.com/3d-nand-flash-wars-begin/), the growth seems exponential. Complex computing logic can't be stacked like this just yet but engineers may soon find a way to stack 2, 4, 8, 2^n ... transistors. (huh, but how do we keep them from melting all the time?)

Now what about that? Is it, or would it be, in tune with Moore's law? I think yes. Various tricks, not just "simple" shrinking of transistors, will help us to get more and more transistors in new phones and servers and smart toasters and everything. As long as this continues, the Law is valid. We don't need a 3D variant of it.
 
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Re: 5 nm chips in 2020

Thu Dec 12, 2019 6:17 pm

just brew it! wrote:
Wirko wrote:
just brew it! wrote:
Wafer-scale integration does not increase density, you're just making bigger chips. Which is bad for yield.

The only current attempt that I know of is Cerebras, and they say they can work around the defective "cells" somehow. Sure they can, and they absolutely have to in order to make a working chip, but some additional logic and interconnects are necessary to do that, plus spare cells.

Yup. And I'm not convinced this will end up being more economical (or more performant) than using some sort of large/dense MCM.

It looks like a solution looking for a problem. It's perfectly possible that it bumps into the right problem one day. It's just not going to crush everyone's problems.
 
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Re: 5 nm chips in 2020

Fri Feb 28, 2020 12:10 pm

https://techreport.com/news/3468916/tsm ... processes/

https://www.taiwannews.com.tw/en/news/3881294
Taiwan Semiconductor Manufacturing Co. (TSMC) said Tuesday it is planning to hire more than 4,000 new staff this year.

7 nanometer process is the latest technology the chipmaker is mass producing. TSMC is scheduled to launch mass production of the 5nm process in the first half of this year. The 3nm process is expected to begin commercial production in 2022.

TSMC has said its capital expenditure for 2020 is expected to range between US$15-16 billion, its highest ever. According to TSMC, it will assign 80 percent of the capex to develop 3nm, 5nm and 7nm technology, 10 percent of spending to advanced packaging and testing technology development and 10 percent to special process development.
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Re: 5 nm chips in 2020

Wed Mar 04, 2020 8:28 pm

https://www.tomshardware.com/news/intel ... ership-5nm
It looks like 2020 and 2021 are going to be long years for Intel. CFO George Davis presented at the Morgan Stanley conference yesterday that the company felt that it would not reach process parity with competitors until it produces the 7nm node at the tail end of 2021.

Davis noted that the company's 10nm node won't be as successful as Intel's prior nodes: "This isn't just going to be the best node that Intel has ever had. It's going to be less productive than 14nm, less productive than 22nm, but we're excited about the improvements that we're seeing and we expect to start the 7nm period with a much better profile of performance over that starting at the end of 2021....but the fact is that I wanted to be clear what was happening during the 10nm generation. The fact is, it isn't going to be as strong a node as people would expect from 14nm or what they'll see in 7nm. ....the effect of 10nm in 2021. It's sort of built today, you've got to get through that product cycle and the node. We're excited about the products, but the node isn't going to be quite the performer that historically we've had."
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Re: 5 nm chips in 2020

Thu Mar 12, 2020 9:20 am

https://www.techpowerup.com/264707/tsmc ... lly-booked
5 nm capacity is fully booked from April onward.
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Re: 5 nm chips in 2020

Sat Mar 14, 2020 8:45 pm

JustAnEngineer wrote:
https://www.techpowerup.com/264707/tsmc-to-kickstart-5-nm-volume-production-in-april-production-capacity-already-fully-booked
5 nm capacity is fully booked from April onward.

Apple moving to 5nm might mean more 7nm capacity for AMD.
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Re: 5 nm chips in 2020

Mon Mar 23, 2020 7:44 pm

https://www.techpowerup.com/264994/tsmc ... t-7nm-node
5NP is 84% more dense than N7. This is what will make Apple's A14.
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Re: 5 nm chips in 2020

Tue Mar 24, 2020 6:23 am

JustAnEngineer wrote:
https://www.techpowerup.com/264994/tsmc-n5p-5nm-node-offers-84-87-transistor-density-gain-over-current-7nm-node
5NP is 84% more dense than N7. This is what will make Apple's A14.


Interesting info on densely but kind of confusing regarding timeline and Apple. It claims 5NP production starts later this year while 5 starts in April. For Apple to use a process for the next iPhone, I’d think production would need to start in April, not later this year.
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Re: 5 nm chips in 2020

Wed Mar 25, 2020 4:55 am

RAM made with EUV imaging is a thing now. Progress continues.
https://www.techpowerup.com/265064/sams ... on-modules
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Re: 5 nm chips in 2020

Wed Mar 25, 2020 11:07 am

JustAnEngineer wrote:
RAM made with EUV imaging is a thing now. Progress continues.
https://www.techpowerup.com/265064/sams ... on-modules


I'm looking forward to DDR5 + Zen4 (the ThreadRipper version). But it sounds like that's 2 years away.
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Re: 5 nm chips in 2020

Tue Apr 14, 2020 6:16 am

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