Personal computing discussed
Moderators: renee, Flying Fox, morphine
Igor_Kavinski wrote:https://www.techspot.com/news/83078-haswell-back-intel-reverses-decision-discontinue-22nm-pentium.html
Haswell, welcome back from the dead
https://wccftech.com/intel-ceo-beyond-cpu-7nm-more/
just brew it! wrote:Aranarth wrote:just brew it! wrote:I believe TSMC's 7nm process is already on EUV.
it is not.
7+ from tsmc will be EUV when it arrives.
Ahh, guess I got 7 confused with 7+!
Wirko wrote:Funny things happen if you apply the ++ operator on the constant 14 enough times.
just brew it! wrote:...some Fortran compilers did not strictly guard against this sort of thing in all situations...
Igor_Kavinski wrote:just brew it! wrote:...some Fortran compilers did not strictly guard against this sort of thing in all situations...
I wonder how many scientists went bald trying to debug their programs using such compilers
just brew it! wrote:Back in the early days (no idea if any modern compilers still have this issue), some Fortran compilers did not strictly guard against this sort of thing in all situations. Arguments to functions were passed by reference, and to conserve scarce memory, all references to the same constant resolved to the same shared copy of that constant. So if you passed a constant as a function argument, and the function subsequently tried to assign something to the argument, you could arbitrarily change the value of a constant (with the new value subsequently being used everywhere in the program until the program was restarted).
Wirko wrote:just brew it! wrote:Back in the early days (no idea if any modern compilers still have this issue), some Fortran compilers did not strictly guard against this sort of thing in all situations. Arguments to functions were passed by reference, and to conserve scarce memory, all references to the same constant resolved to the same shared copy of that constant. So if you passed a constant as a function argument, and the function subsequently tried to assign something to the argument, you could arbitrarily change the value of a constant (with the new value subsequently being used everywhere in the program until the program was restarted).
If each reference takes up, say, 16 bits, and an integer constant takes up 16 bits too, how much of that scarce memory do you save?
just brew it! wrote:Wirko wrote:Funny things happen if you apply the ++ operator on the constant 14 enough times.
Indeed. Especially given that applying an operator that expects an lvalue to a constant isn't going to end well.
Geek trivia tangent:
Back in the early days (no idea if any modern compilers still have this issue), some Fortran compilers did not strictly guard against this sort of thing in all situations. Arguments to functions were passed by reference, and to conserve scarce memory, all references to the same constant resolved to the same shared copy of that constant. So if you passed a constant as a function argument, and the function subsequently tried to assign something to the argument, you could arbitrarily change the value of a constant (with the new value subsequently being used everywhere in the program until the program was restarted).
The running joke was something to the effect of "Have you ever accidentally (or intentionally) changed the value of 1?" Talk about bizarre, difficult-to-diagnose bugs...
This is the first mention on 1.4nm in the context of Intel on any Intel-related slide. For context, if that 1.4nm is indicative of any actual feature, would be the equivalent of 12 silicon atoms across.
Jim Keller, Senior Vice President of Intel’s Silicon Engineering Group said Tuesday at MIT Technology Review’s Future Compute conference that Moore’s Law — a refresher definition is below — won’t be dead for at least another 30 years or so.
Igor_Kavinski wrote:Jim Keller, Senior Vice President of Intel’s Silicon Engineering Group said Tuesday at MIT Technology Review’s Future Compute conference that Moore’s Law — a refresher definition is below — won’t be dead for at least another 30 years or so.
WTH????!
Igor_Kavinski wrote:https://www.anandtech.com/show/15217/intels-manufacturing-roadmap-from-2019-to-2029This is the first mention on 1.4nm in the context of Intel on any Intel-related slide. For context, if that 1.4nm is indicative of any actual feature, would be the equivalent of 12 silicon atoms across.
https://www.inverse.com/article/61384-m ... re-computeJim Keller, Senior Vice President of Intel’s Silicon Engineering Group said Tuesday at MIT Technology Review’s Future Compute conference that Moore’s Law — a refresher definition is below — won’t be dead for at least another 30 years or so.
WTH????!
blastdoor wrote:that's not exactly a cheat but it's not not a cheat either.
Wirko wrote:blastdoor wrote:that's not exactly a cheat but it's not not a cheat either.
D'oh. So it's a quantum cheat.
What about 2D integration, for example wafer scale integration? Is that cheating or not or not not? Moore's law is just "the observation that the number of transistors in a dense integrated circuit doubles about every two years" (Wikipedia) and you can't say today's ICs aren't dense.
Wirko wrote:What about 2D integration, for example wafer scale integration? Is that cheating or not or not not? Moore's law is just "the observation that the number of transistors in a dense integrated circuit doubles about every two years" (Wikipedia) and you can't say today's ICs aren't dense.
just brew it! wrote:Wafer-scale integration does not increase density, you're just making bigger chips. Which is bad for yield.
Wirko wrote:just brew it! wrote:Wafer-scale integration does not increase density, you're just making bigger chips. Which is bad for yield.
The only current attempt that I know of is Cerebras, and they say they can work around the defective "cells" somehow. Sure they can, and they absolutely have to in order to make a working chip, but some additional logic and interconnects are necessary to do that, plus spare cells.
blastdoor wrote:Seems like 2d integration is kind of a one-off that isn't going to double density every 24 months for the next 30 years, or am I misunderstanding what you mean?
The reason I say 3d stacking both is and is not a cheat is that Moore's Law is silent regarding the 3rd dimension. It only talks about transistor density within a 2d area. Counting transistors stacked above as an increase in 2d density isn't specifically ruled out in the Law, and so it's not exactly a cheat. But it sure does seem to violate the spirit of the Law as commonly understood, so it's not not a cheat either.
A 3d Moore's Law would probably focus on density of transistors within a volume, rather than an area, and so 3d stacking would not represent an improvement.
just brew it! wrote:Wirko wrote:just brew it! wrote:Wafer-scale integration does not increase density, you're just making bigger chips. Which is bad for yield.
The only current attempt that I know of is Cerebras, and they say they can work around the defective "cells" somehow. Sure they can, and they absolutely have to in order to make a working chip, but some additional logic and interconnects are necessary to do that, plus spare cells.
Yup. And I'm not convinced this will end up being more economical (or more performant) than using some sort of large/dense MCM.
Taiwan Semiconductor Manufacturing Co. (TSMC) said Tuesday it is planning to hire more than 4,000 new staff this year.
7 nanometer process is the latest technology the chipmaker is mass producing. TSMC is scheduled to launch mass production of the 5nm process in the first half of this year. The 3nm process is expected to begin commercial production in 2022.
TSMC has said its capital expenditure for 2020 is expected to range between US$15-16 billion, its highest ever. According to TSMC, it will assign 80 percent of the capex to develop 3nm, 5nm and 7nm technology, 10 percent of spending to advanced packaging and testing technology development and 10 percent to special process development.
It looks like 2020 and 2021 are going to be long years for Intel. CFO George Davis presented at the Morgan Stanley conference yesterday that the company felt that it would not reach process parity with competitors until it produces the 7nm node at the tail end of 2021.
Davis noted that the company's 10nm node won't be as successful as Intel's prior nodes: "This isn't just going to be the best node that Intel has ever had. It's going to be less productive than 14nm, less productive than 22nm, but we're excited about the improvements that we're seeing and we expect to start the 7nm period with a much better profile of performance over that starting at the end of 2021....but the fact is that I wanted to be clear what was happening during the 10nm generation. The fact is, it isn't going to be as strong a node as people would expect from 14nm or what they'll see in 7nm. ....the effect of 10nm in 2021. It's sort of built today, you've got to get through that product cycle and the node. We're excited about the products, but the node isn't going to be quite the performer that historically we've had."
JustAnEngineer wrote:https://www.techpowerup.com/264707/tsmc-to-kickstart-5-nm-volume-production-in-april-production-capacity-already-fully-booked
5 nm capacity is fully booked from April onward.
JustAnEngineer wrote:https://www.techpowerup.com/264994/tsmc-n5p-5nm-node-offers-84-87-transistor-density-gain-over-current-7nm-node
5NP is 84% more dense than N7. This is what will make Apple's A14.
JustAnEngineer wrote:RAM made with EUV imaging is a thing now. Progress continues.
https://www.techpowerup.com/265064/sams ... on-modules
