The problem with RISC-V is that the target markets — small companies looking for extreme customization — simply may not be big enough to ever spark much in the way of toolset development, familiarity, or cost savings. How many companies both want to build their own extremely customized architecture and can afford to hire the engineers that would do the job more ably that a default Cortex-A5 CPU from ARM? Our guess is not many. This leaves RISC-V in an uneasy no-man’s land — the engineers with the expertise to build the products are most likely familiar with other ecosystems, while the companies that would most benefit from the cost savings and customized features can’t afford the engineers.
just brew it! wrote:JBI, I completely agree with this comment. But, just to amplify it a bit, not only with the h/w, but also with the entire s/w ecosystem. I submit that these days, a new architecture needs to win by at least an order of magnitude in performance and/or power and/or (some new) capability to have a chance at success.critical mass
MarkG509 wrote:just brew it! wrote:critical mass
JBI, I completely agree with this comment. But, just to amplify it a bit, not only with the h/w, but also with the entire s/w ecosystem. I submit that these days, a new architecture needs to win by at least an order of magnitude in performance and/or power and/or (some new) capability to have a chance at success.
And even then, only if the ecosystem exists and is well tested.
The Egg wrote:I think there best move would be to donate large quantities of this technology to universities for free, that way kids entering this field will be more likely to learn/use/develop with it because it was freely available at an opportune time.
ronch wrote:I think this is more of a software issue. I would think the hardware part is pretty much taken cared of. Take Nvidia's GPUs for example. Nvidia's GPUs can support x86 host processors as well as ARM. There may be some minor low level work to do but the entire GPU is probably left intact. The same goes for peripheral interfaces such as SATA controllers, USB controllers, etc. But the one thing RISC-V (or any other ISA) need to do is be able to connect to a specific external bus. Take the old Socket 7 bus, for example. A lot of different CPUs plugged into it and although they were all x86, they were based on entirely different internal microarchitectures that simply knew how to talk to the Super 7 Pentium bus architecture. So if RISC-V systems will be built, they will need to adopt the particular microarchitecture using the ISA to a particular bus, say, HyperTransport, seeing as they could license it. This is where software comes in as the new CPU will need to be aware of the things you plug into the same system. AFAIK all, if not most, general purpose processors are hardware-agnostic concerning connecting to external devices, and most peripheral devices are also CPU-agnostic in term of hardware. It's all a matter of vendors providing the drivers written in a language the CPU will accept to control the peripherals.