As far as die sizes go, it is really weird looking at Haswell and trying to scale up: Intel doesn't use the entire die are in some versions. That complicates the hypothetical picture and makes any rough estimate, well rough. So here are the dies sizes (source
Haswell 2C GT3 = 177 mm^2
Haswell 4C GT3 = 264 mm^2
Haswell 4C GT2 = 181 mm^2
Haswell 2C GT2 = 130 mm^2
Going from GT2 to GT3 (adding 20 EUs) adds 41 mm^2 of die space.
Going from dual to quad core adds 37 mm^ 2 of die space.
Uncore in the 2C GT2 configuration would be 52 mm^2.
I'd guesstimate that a 160 EU part would around 400 mm^2 with a wide GDDR5 memory bus. Note that I'm rounding up quite a bit to account for additional ROPs, TMUs and wider memory bus necessary to scale. Cranking up the base clock speeds to 1.3 Ghz base with turbo up to 1.6 Ghz give it another boost. The dedicated GDDR5 memory bus would address the bandwidth issue which would allow us to use GT3e the baseline instead of the vanilla GT3. Assuming perfect linear scaling, we'd be looking at a part roughly 5 times faster than GT3e in terms of compute. Even with these performance bumps, I just don't see it being competitive with the top of the line from AMD or nVidia. Putting such a chip up against the R9 280X or GTX 770 would be interesting and something that Intel could be far more competitive with (the R9 280X is about 5.5 times faster in theoretical compute).
I'm not even going to attempt to tackled the concept of power consumption. Haswell is a very power optimized design and their 84W desktop allocation is shared between the CPU and GPU. The dynamic nature make its it very difficult to determine just how much of that power consumption is due to just the GPU. Even then, they do have a power envelope of 300W to work in the PCI-e spec which is 3.5 times more. I fathom that my 160 EU part above would fit into the 300W spec but I don't know if it'd go below 225W for a 6 + 6 pin configuration under load. On the flip side, I'd argue that Intel would have better idle power consumption than either AMD or nVidia.
Then again, Intel has fab space to use and the next Xeon Phi is estimated to be around 700 mm^2
before the eDRAM is factored in. Scaling the number of EU's to 300 along with other units would be around 700 mm^2 by my guestimation. Toss in some of Intel's fast eDRAM and having 500 GB/s of bandwidth is feasible. Such a design would be performance competitive with the best from AMD and nVidia but also radically more expensive. Large dies like that are not cheap, inherently have poor yields plus the eDRAM only adds more to the cost. So ultimately if Intel really, really wanted to, I believe that they could take the performance crown but it would be a Pyrrhic victory.