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I'm confused as all hell right now. Take the Z490 chipset for example. There is a block diagram for this chipset that has a line connected to the chipset that says up to 24 lanes for PCI-E 3.0. On the same diagram there are three separate lines connected to the CPU that say 1x16 or 2x8 or (1x8 and 2x4). Are the max of 24 lanes for the chipset separate from the 16 lanes through the CPU? The way I was interpreting the chipset at first is that if I have a video card in, that would take up 16 and then I would only have 8 remaining but that just doesn't seem right. Could someone clarify this for me?

As far as I understand, the separate 16 lanes are directly from the CPU.

For the last couple of normal desktop platforms from Intel. The CPU itself has a PCIe controller that drives up to 16 PCIe lanes and an additional 8 PCIe lanes are driven by the PCIe controller on the PCH. The PCH is linked to the CPU through a DMI. It is a similar setup on the last couple of AMD platforms but their southbridge use a PCIe link to talk to CPU.

Isn't it 16 + 24 = 40 lanes?

An AnandTech article says:

The Z490 chipset and Intel 10th Generation Comet Lake desktop processors have a total combined PCIe count of 40, which is 16 from the CPU and 24 from the chipset.

It's 16 from the CPU directly and an additional 24 off the chipset that share the DMI/QPI/whateverthehelltheycallitnow bandwidth between the chipset and the CPU.

Waco wrote:

It's 16 from the CPU directly and an additional 24 off the chipset that share the DMI/QPI/whateverthehelltheycallitnow bandwidth between the chipset and the CPU.

Intel now calls their CPU interconnect UPI for their HEDT/server platforms. I thought they didn't implement it on their normal desktop platforms and used the DMI.

I don't know, I haven't kept track.