AMD's Rev. G core more than a simple die shrink?
The Inquirer has put up an interesting article about AMD's
plans for the Rev. G K8 core, which is due to succeed the current
Rev. F as AMD moves to 65 nm process technology late this year.
According to The Inquirer, Rev. G will not merely be a die shrink; instead, AMD will tweak the design to increase the number of
instructions per clock, thereby enabling better performance. To back this prediction,
The Inq links to this anonymous
page that compares die photos of a Rev. F core and a Rev. G core.
The site claims the Rev. G core's instruction fetch area appears to sport an
extra complex decoder, upping the total number of decoders from three to
four. The Rev. G die shot also reveals some extra logic above and below
the data cache area. The author of the page speculates these two logic
chunks to be an out-of-order load/store buffer and an out-of-order L2
read/write buffer, respectively.
Factoring in AMD's new process technology improvements, The Inquirer
says Rev. G processors will have the potential for both higher
instructions per clock and higher clock speeds. These factors could make
Rev. G a good stepping stone to the so-called K8L, AMD's real next-gen architecture,
and increase competitiveness against Intel's Core 2 chips. However, The
Inquirer believes Rev. G's improvements will likely not be enough for
AMD to regain the performance lead over the Core 2 Duo and Core 2 Extreme.