All things must come to an end, it seems: both The Inquirer and X-bit labs now report that AMD has no plans for a reverse-HT feature. The Inq denies the technology's existence completely, while X-bit labs' source says there is no such implementation in AMD's current dual-core processors. To top off these reports, Jon "Hannibal" Stokes from Ars Technica has attempted to debunk initial claims about reverse-HT.
First off, there's no way this would work the way the author [of one of the stories] seems to think it would. How would the cores' pipelines support this in any phase of execution? In the fetch phase, there would have to be some arbitration mechanism whereby the two cores fetched alternate instruction blocks from the I-cache, thus distributing the instruction stream across two processors.Stokes closes in saying that attempting to go into detail about the rumored tech is akin to "asking how Superman could lift an entire continent up into space without it breaking apart."
Then, once the instruction stream is fragmented inside the two cores, how are the register files kept in sync? If an add in one line of code writes its result to a register in one core, then how could a test instruction in the other core read that distant register to see if it needs to branch? Or how would out-of-order execution work across two cores? Would the instruction schedulers have their own separate bus to communicate over?