HP uses nanowires to make denser, cooler FPGAs

Researchers at HP Labs have devised a new technology that could pave the way for field programmable gate arrays (FPGAs)—programmable logic chips, in layman's terms—800% denser and yet still cooler-running than current FPGAs. This technology, which the researchers christened field programmable nanowire interconnect (FPNI), "calls for a nanoscale crossbar switch structure to be layered on top of conventional CMOS [Complementary Metal-Oxide Semiconductor]."
In the FPNI approach, all logic operations are performed in the CMOS, whereas most of the signal routing in the circuit is handled by a crossbar that sits above the transistor layer. Since conventional FPGAs use 80 to 90 percent of their CMOS for signal routing, the FPNI circuit is much more efficient; the density of transistors actually used for performing logic is much higher and the amount of electrical power required for signal routing is decreased.

The researchers presented a "conservative" chip model using 15-nanometer-wide crossbar wires combined with 45-nm half-pitch CMOS, which they said they believe could be technologically viable by 2010. That would be equivalent to leaping ahead three generations on the International Technology Roadmap for Silicon without having to shrink the transistors, they said.

According to HP Labs researchers Greg Snider and Stan Williams, HP is currently developing a chip that uses FPNI technology, and the prototype could be complete "within the year." Companies like AMD and Intel might not scramble to license and implement the technology, though. FPGAs are typically used for prototyping and by fabless companies who can't afford to produce their own chips, although they also have uses in other areas, such as cryptography.
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