The i850 Tehama will cost $75 + $5 for the firmware hub component (most chipsets cost $30 or less) and come with a 6-layer design, while PC800 RDRAM prices may increase due to lack of demand for PC600 and PC700. Intel will be enticing OEMs to keep P4 / RDRAM systems at $2000 or less by offering a $70 "Rambus rebate deal" until Brookdale in '01.
Both Willamette and Northwood will use a 128-byte cache line vs. the PIII's 32, resulting in long burst external bus transactions. In order to widen the performance delta of the P4, Intel will 'cripple' Tualatin by initially releasing with a 133MHz bus. The 0.13 micron process PIII will ship in FC-PGA2 with integrated heat spreader, thus rendering it incompatible with today's mobos. Prior to that, a new stepping of the PIII dubbed "Coppermine-T" will enable better ramps and a 1GHz mobile PIII.
The Celeron-128 will reach 800/66 in Q1 before ramping to a 100MHz bus for higher speeds, but since Intel will be concentrating its efforts in the PIII and P4 arenas, availability will be constrained. Here are some more interesting points and speculations:
- Intel and MadOnion to release 3DMark 2001 'optimized' for P4
- CliBench scores from 2CPU have been reposted
- P4 has edge over Athlon in MP3 audio file encoding
- Intel to withhold DDR capabilities of Almador?
- Almador Display Cache Controller to use RDRAM (16MB Media-RIMM for Z-buffer use?)
Enough. Highly recommended reading.