U.S. military contractor Raytheon has developed a processor whose architecture can optimize itself on-the-fly depending on what it needs to run, according to a report by Military Embedded Systems. Raytheon developed the processor, which it dubbed MONARCH (short for Morphable Network Micro-Architecture), for the U.S. Department of Defense in order to handle the large amounts of data and processing required by sensor systems.
“Typically, a chip is optimally designed either for front-end signal processing or back-end control and data processing,” explained Nick Uros, vice president for the Advanced Concepts and Technology group of Raytheon Space and Airborne Systems. “The MONARCH micro-architecture is unique in its ability to reconfigure itself to optimize processing on the fly. MONARCH provides exceptional compute capacity and highly flexible data bandwidth capability with beyond state-of-the-art power efficiency, and it’s fully programmable.”
A diagram of MONARCH posted by Military Embedded Systems says the chip has six RISC cores with 2MB of on-chip DRAM each, 12 arithmetic clusters, 31 memory clusters, two 8GB/s memory interfaces, two RapidIO serial interfaces, 17 DIFL ports with 2.6GB/s of bandwidth each, and an on-chip 40GB/s data ring. The site says the chip can compute 64 billion floating point operations per second with 60GB/s of memory bandwidth and 43GB/s of off-chip (presumably interconnect) bandwidth. According to Raytheon, the chip outperforms Intel’s quad-core Xeon processors “by a factor of 10.”
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