Intel's Pat Gelsinger unveiled some basics about Nehalem for the first time today, and in doing so, he called it the first truly dynamically scalable microarchitecture. We don't yet know entirely what that means, but Gelsinger predicted the character of the architecture will become clearer as Intel discloses more about it. Here's what we know about Nehalem now.
- Has roots in the Core microarchitecture — To be precise, Gelsinger stated that the new architecture "leverages" the four-issue-wide, er, core of the Core microarchitecture.
- An on-die memory controller with P2P interconnects — What the Hector? Yep, Intel admits it's going for an integrated memory controller much like AMD's. Nehalem's memory controller will be designed to interface with DDR3 memory, which should be the standard in the market by the time these CPU products arrive. Intel will provide a version of its memory controller to support buffered DIMMs for server configs, as well.
In addition, Nehalem will ditch the front-side bus for a series of point-to-point interconnects, presumably similar to AMD's HyperTransport technology.
- Intel's own brand of fusion — Not content to ape AMD's basic system architecture, Intel will also emulate AMD's Fusion initiative by moving its integrated graphics core from the north bridge to the CPU socket for "mainstream" client PCsthink Centrino laptops and vPro corporate desktops. We don't yet know whether the graphics core will be integrated directly into the processor die or placed in a multi-chip arrangement like Intel's current quad-core processors are. We also don't know how many CPU cores will potentially coexist with a GPU at once. Gelsinger would only say that graphics will be "in the processor socket."
- Hyper-Threading is back! — It may or may not be called Hyper-Threading, but Nehalem will have a similar simultaneous multithreading capability. Each processing core on the chip will have two front-ends, much like the Pentium 4 did. That means a quad-core version of Nehalem would be able to execute eight threads in parallel.
- A multi-level shared cache architecture — I suppose one could say Core 2 Duo has a "multi-level shared cache architecture," but reading between the lines, I believe Gelsinger may have been signaling the potential addition of an L3 cache level which could be shared between cores.
- Something called "Performance enhanced dynamic power management" — Penryn's dynamic acceleration is impressive in its own right, but Gelsinger said this one would involve "new, undisclosed technologies." We don't yet know what those are.
- A native 45nm design — Intel claims Nehalem will "fully unlock" the benefits of its 45nm high-K fab process because it's a native 45nm design, not a die-shrink.
- Scalable configurations — The new architecture can scale from one to eight cores and, correspondingly from one to 16 simultaneous threads (at a peak of two threads per core). Its cache architecture is similarly scalable, allowing Intel to create a large family of products based on this design.