Intel's Tera-scale chip dissected

David Kanter over at Real World Technologies has sat down and put together a pretty detailed and rather interesting article about Intel's 80-core "Tera-scale" processor. As a reminder, the chip is more of a research project than an upcoming design, but Intel nevertheless showed it off at the Integrated Solid State Circuits Conference a couple of months ago and boasted that it could crunch a trillion floating point operations per second (teraFLOPS). Kanter's article covers the Tera-scale processor's specs and design then delves into the nitty-gritty details of the chip's internal networking aspect and power-saving techniques.

According to Kanter, the Tera-scale chip's main attraction is its network and router design as well as its "mesochronous" interfaces and clock distribution. Each of the chip's 80 cores (or "tiles") has a five-port, dual-lane router with a shared crossbar and 80GB/s of aggregate communication bandwidth. The Tera-scale chip also uses "mesochronous" clocking (whereby frequency is the same but signal phase differs) for interfaces between routers, which allows Intel to use a less power-hungry clock distribution network. Kanter concludes that Intel's mesochronous clocking and network design is interesting, and that it offers the opportunity to cut power consumption by a significant amount. However, he says the design is "not quite ready for implementation in mainstream x86 [processors]."

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