Intel clearly has to hop on the GPU bandwagon, but the question is with what. To answer that, the presentation outlines an architecture that could very well appear in Intel's upcoming discrete graphics processors. This architecture is based on quad-threaded, in-order "throughput cores" that have a 10mm² die area and consume only 6.25W of power each. Those cores each have a 16-wide (512-bit) vector unit and can execute VLIW instructions.
The presentation shows a chip diagram made up of 10 such cores plus 4MB of shared cache. The chip would have a 140mm² die area, 90W power consumption, and it would supposedly be capable of 1.2 teraFLOPS of performance. The next couple of slides show a similar core diagram but with fixed instruction units on one side and high-bandwidth memory I/O on the other. Off-die bandwidth for the core would be somewhere above 150GB/s, the slides say, while aggregate on-die bandwidth would be a whopping 1TB/s.