The technique creates a vacuum between copper wires on a chip, allowing electrical signals to flow faster while consuming less power. The self-assembly process enables the nanoscale patterning required to form the gaps, and this patterning is considerably smaller than current lithographic techniques can achieve.IBM boasts the technology can either allow electrical signals to flow 35% faster or cut energy consumption by 15% compared to chips made using conventional techniques. Furthermore, the technology "can be incorporated into standard CMOS manufacturing lines without disrupting operations or retooling." EE Times says IBM intends to introduce this "airgap" technology into its 32nm process. Chips based on that process are expected to start rolling out of IBM's Fishkill, New York-based fab in 2009.
The IBM researchers said a vacuum is the ultimate insulator for wiring capacitance, which occurs when two conductors, in this case adjacent wires on a chip, siphon electrical energy from one another, generating undesirable heat and slowing the speed at which data can move through a chip.