AMD preps instructions to aid software parallelism
EETimes has the scoop
on AMD's plans to extend the x86 instruction set in order to allow programs to make better use of parallel execution via multiple threads. The company has announced two new instructions intended to "give software access to information about cache misses and retired instructions so they can optimize data structures for better performance," says the report, and these instructions are the first fruits of a larger effort dubbed Extensions for Software Parallelism. The two new instructions and a new data structure will enable what AMD calls "Light-Weight Profiling" (LWP), allowing runtime environments like .NET and Java to make on-the-fly adjustments in order to avoid cache misses and otherwise optimize performance. The LWP spec is already available here
on AMD's website.