The basic idea behind Raw, a project that was started well before Moore's Law stopped delivering huge clockspeed increases, was that as the number of transistors on a chip increases, wire delay becomes an architecturally significant factor in chip design. The Alpha 21164, Pentium 4, and PowerPC 970 are all examples of the first wave of commodity processors that had made major microarchitectural concessions (i.e., dedicated pipeline stages and increased load-use latencies for certain sequences of integer operations) for wire delay, but the effects of wire delay were still hidden from programmers as far as possible.TILE64 will debut at clock speeds between 600MHz and 900MHz and first be made available on PCI Express daughterboards.
Agarwal's idea was to expose wire delay to programmers via the ISA. The Raw project, the name of which seems to be a recursive acronym for "Raw Architecture Workstation," exposes wire delay to the programmer as hops on an on-chip mesh network. It takes one cycle for data to move from one tile to the next, with the result that a compiler can statically schedule operations among multiple tiles' ALUs by taking into account the exact number of cycles that it takes for a result to propagate across the chip.