AMD aims SSE5 instruction set for 2009

So far, AMD has largely been playing catch-up with the various iterations of the SSE instruction set. SSE2 support made it into AMD’s desktop lineup with the Athlon 64 nearly three years after the Pentium 4 launch, and AMD users had to wait about a year for SSE3 to find its way into new Athlon 64 steppings after “Prescott” Pentium 4s rolled out. Intel is now about to unveil SSE4 with its new 45nm Penryn chips, but AMD is already thinking one step ahead: the company has announced it is developing a new instruction set called SSE5.

AMD says SSE5 “helps maximize the output of each instruction and consolidates code base by introducing functionality previously only found in specialized, high-performance architectures, to the x86 platform.” According to the press release, such functionality includes:

  • 3-Operand Instructions A computing instruction is executed by applying a mathematical or logical function to operands, or inputs. By increasing the number of operands an x86 instruction can handle from 2 to 3, SSE5 enables the consolidation of multiple, simple instructions into a single, more effective instruction. The ability to execute 3-Operand Instructions is currently only possible on certain RISC architectures.
  • Fused Multiply Accumulate The 3-Operand Instruction capability enables the creation of new instructions which efficiently execute complex calculations. The Fused Multiply Accumulate instruction combines multiplication and addition to enable iterative calculations with one instruction. The simplification of the code enables rapid execution for more realistic graphics shading, rapid photographic rendering, spatialized audio, complex vector mathematics and other performance-intense applications.
  • More information about SSE5 is available on this page on AMD’s Developer Central site. AMD says it’s making technical details about SSE5 available to the developer community early in order to “foster an industry dialogue and solicit feedback.”

    According to AMD, SSE5 is scheduled to make its first appearance in the upcoming “Bulldozer” core, which will become available in 2009. Bulldozer will be at the heart of Fusion, AMD’s upcoming microprocessor/graphics processor chimera, as well as upcoming eight- and 16-core high-end microprocessors.

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