Intel Developer Forum — In his opening keynote speech at Fall IDF today, Intel CEO Paul Otellini revealed new details about the firm's next-generation CPU microarchitecture, code-named Nehalem. The design is now complete, and Otellini claimed it's on track for delivery in the second half of 2008. In fact, he displayed a wafer of Nehalem chips and reported that each chip will be comprised of approximately 731 million transistors.
Chief architect Glenn Hinton made an appearance in order to demo a working Nehalem-based system, just three weeks old, running Windows XP. Otellini also claimed the team managed to get Mac OS X booting just today.
In its "largest configuration," Nehalem will pack eight CPU cores onto a single die. Each of those cores will present the system with two logical processors and be able to execute two threads via simultaneous multithreading (SMT)—a la HyperThreading. So a single Nehalem chip will be able to execute 16 threads at once.
Hinton said the design team put quite a bit of effort into improving single-threaded performance in Nehalem, and claimed that each feature added to the chip had to meet stringent power-efficiency guidelines, as well. Nehalem will integrate a high-performance memory controller and a new chip-to-chip interconnect known as QuickPath—both provisions similar to AMD's Opteron processors.
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