Kanter dissects Nehalem

If you're curious about Intel's next-generation Nehalem processors, David Kanter from Real World Technologies has written a thorough dissection of Nehalem's architecture. The article discusses everything from Nehalem's memory controller and cache setup to the nitty-gritty features of its execution units.

Needless to say, readers not at least partially fluent in processor architecture jargon probably may want to abstain. Nonetheless, the article contains plenty of interesting insights about what we can expect from Intel's next major architecture. For instance, Kanter says Nehalem's local memory latency is about 60% that of current 5400-series Xeons with 1600MHz FSBs, and he infers that the actual latency should be about 60 ns.

Kanter also goes into estimates of Nehalem's performance. He says the upcoming architecture will only yield minor gains over Core 2 in non-bandwidth-dependent workloads like integer applications, but he expects Nehalem's performance in floating-point and high-performance computing applications should be "nothing short of a miracle – with performance gains of 2X or better."

Nehalem chips are scheduled to ship in the fourth quarter of this year, and the rumor mill pegs the release of mainstream desktop variants in the first half of 2009. If the systems Intel had on display at the Intel Developer Forum in Shanghai yesterday are any indication, quad-core Nehalem chips will be able to run at 3.2GHz.

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