The HardOCP gets very, very hard read—if you're not an engineer. The HardOCP has published what looks like an academic paper entitled Filling the CPU Pipelines, the Quest for Lower Latencies. From what I've read so far, it's proposing a modified version of SDRAM (of DDR ESDRAM, actually) that might promise lower latencies without much extra cost. Written by Michael Scheutte of LostCircuits, it's a satifying read if you're willing to sift through some technical history and jargon. I'm not sure what I think of it all just yet, but it's definitely recommended reading. Thoughts?
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